Devices and methods including an etch stop protection material

Abstract

Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

1 . (canceled) 
     
     
         2 . A method, comprising:
 forming an etch stop material over a substrate;   forming alternating conductive tiers and dielectric tiers above the etch stop material;   forming a trench extending through the alternating conductive tiers and dielectric tiers to the etch stop material;   forming polysilicon extending within the trench and contacting the etch stop material;   at least partially oxidizing the polysilicon within the trench; and   removing at least a portion of the oxidized polysilicon contacting the etch stop material.   
     
     
         3 . The method of  claim 2 , further comprising:
 recessing the conductive tiers relative to the dielectric tiers to form recesses in which the remaining material of the conductive tiers forms respective memory cell control gates, wherein the formed polysilicon extends within the recesses as well as in contact with the etch stop material.   
     
     
         4 . The method of  claim 3 , further comprising:
 forming a nitride material on the at least partially oxidized polysilicon; and   removing at least a portion of the nitride material to form a nitride structure within the recesses.   
     
     
         5 . The method of  claim 2 , wherein the etch stop material comprises a metal oxide. 
     
     
         6 . The method of  claim 5 , where the metal oxide is selected from aluminum oxide, zirconium oxide, hafnium oxide, silver oxide, iron oxide, chromium oxide, titanium oxide, copper oxide, and zinc oxide. 
     
     
         7 . The method of  claim 2 , wherein oxidizing the polysilicon within the trench comprises performing an in-situ steam generation oxidation process to oxidize exposed polysilicon within the trench. 
     
     
         8 . The method of  claim 2 , wherein the remaining oxidized polysilicon forms at least part of an inter-poly dielectric layer of a memory cell and contacts at least a portion of the etch stop material. 
     
     
         9 . The method of  claim 8 , further comprising:
 recessing the conductive tiers relative to the dielectric tiers to form recesses in which the remaining material of the conductive tiers forms respective memory cell control gates;   wherein the formed polysilicon extends within the recesses as well as in contact with the etch stop material.   
     
     
         10 . The method of  claim 9 , further comprising:
 forming a nitride material on the at least partially oxidized polysilicon; and   removing at least a portion of the nitride material to form nitride structures within the recesses, wherein the oxidized polysilicon protects the etch stop layer from damage during the removal of the nitride material.   
     
     
         11 . The method of  claim 10 , wherein the etch stop layer is metal oxide and removing at least a portion of the nitride material comprises performing an acid etch. 
     
     
         12 . The method of  claim 11 , where the metal oxide is selected from aluminum oxide, zirconium oxide, hafnium oxide, silver oxide, iron oxide, chromium oxide, titanium oxide, copper oxide, and zinc oxide. 
     
     
         13 . The method of  claim 10  wherein removing at least a portion of the nitride material comprises performing an acid etch. 
     
     
         14 . A method, comprising:
 forming a metal oxide etch stop material over a substrate;   forming alternating conductive tiers and dielectric tiers above the metal oxide etch stop material;   forming a trench extending vertically through the alternating conductive tiers and dielectric tiers and at least partially into the etch stop material;   horizontally recessing the conductive tiers relative to the dielectric tiers to form recesses in which the remaining material of the conductive tiers forms respective memory cell control gates;   forming a layer of polysilicon extending within the trench and contacting exposed etch stop material within the trench, wherein the formed polysilicon extends within the recesses as well as in contact with the etch stop material;   at least partially oxidizing the polysilicon within the trench to form a layer of oxidized polysilicon vertically above the exposed etch stop layer;   forming a nitride material on the at least partially oxidized polysilicon, wherein the formed nitride material extends within the recesses;   removing at least a portion of the nitride material using acid to form a nitride structures within the recesses, wherein the layer of oxidized polysilicon protects the metal oxide etch stop layer from the acid during the removal of the nitride material; and   removing at least a portion of the oxidized polysilicon contacting the metal oxide etch stop material and the underlying metal oxide layer to expose the substrate.   
     
     
         15 . The method of  claim 14  where removing the portion of the nitride material uses a hot phosphoric acid. 
     
     
         16 . The method of  claim 14 , wherein the remaining oxidized polysilicon within the recesses and the nitride structures within the recesses form at least part of an inter-poly dielectric layer of a memory cell, and wherein the remaining oxidized polysilicon extends through the trench to contact at least a portion of the etch stop material. 
     
     
         17 . The method of  claim 14 , where the metal oxide is selected from aluminum oxide, zirconium oxide, hafnium oxide, silver oxide, iron oxide, chromium oxide, titanium oxide, copper oxide, and zinc oxide. 
     
     
         18 . The method of  claim 14 , wherein oxidizing the polysilicon within the trench comprises performing an in-situ steam generation oxidation process to oxidize exposed polysilicon within the trench.