Negative kick on bit line control transistors for faster bit line settling during sensing

Abstract

A memory device and associated techniques improve a settling time of bit lines in a memory device during a read or verify operation. Bit line control (BLC) transistors in the sense circuits are briefly turned off during a sensing process. After the read voltage on a selected word line is changed to a second word line level or higher, a control gate voltage of the BLC transistor is lowered, helping to inhibit a current flow from a sense circuit through a bit line when a voltage of the bit line is settling. The voltage of the bit line may be settling in response to a memory cell coupled to the selected word line undergoing a transition from off to on. A settling time of the bit line is shortened by stopping the current flow from the sense circuit. Transition of the memory cell from off to on is also improved.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a set of memory cells; and   a control circuit coupled to the set of memory cells, the control circuit comprising:   a row decoder circuit configured to apply a read voltage to a selected word line coupled to the set of memory cells; and   a current sense circuit configured to, in response to the applied read voltage, set a selected bit line of a memory cell to float.   
     
     
         2 . The apparatus of  claim 1 , wherein:
 the current sense circuit is configured to set the selected bit line of the memory cell to float during a settling of the voltage of the selected bit line.   
     
     
         3 . The apparatus of  claim 2 , wherein:
 the current sense circuit is further configured to couple the selected bit line of the memory cell to a current flow from the current sense circuit before performing current sensing.   
     
     
         4 . The apparatus of  claim 3 , wherein the selected bit line of the memory cell is coupled to the current flow from the current sense circuit by a bit line control transistor. 
     
     
         5 . The apparatus of  claim 1 , wherein the current sense circuit is configured to inhibit current flow from the sense circuit through the selected bit line by a factor of about 10 such that a settling time of the voltage of the selected bit line is shortened. 
     
     
         6 . The apparatus of  claim 1 , wherein:
 the row decoder circuit is configured to apply a set of increasing read voltages to the selected word line during a sequential read operation; and   the current sense circuit is configured to set the bit line of the memory cell to float in response to a second read voltage applied to the selected word line following a first read voltage in the set of increasing read voltages.   
     
     
         7 . The apparatus of  claim 1 , wherein:
 during the current sensing, the current sense circuit is configured to determine a cell current which flows through the memory cell and sinks into a source; and   the memory cell transitions from a non-conductive state to a conductive state.   
     
     
         8 . An apparatus, comprising:
 a control circuit coupled to a set of memory cells, the control circuit configured to:   increase a level of a read voltage on a selected word line coupled to the set of memory cells; and   after the increase in the level of the read voltage, set a selected bit line of a memory cell to float.   
     
     
         9 . The apparatus of  claim 8 , wherein the control circuit is configured to set the selected bit line of the memory cell to float during a settling of a voltage of the selected bit line. 
     
     
         10 . The apparatus of  claim 8 , wherein a duration for floating of the selected bit line of the memory cell is predetermined. 
     
     
         11 . A system comprising:
 a set of memory cells connected to a word line and a plurality of bit lines; and   a control circuit coupled to the set of memory cells and configured to perform a sequential read operation on the set of memory cells, the control circuit comprising:   a row decoder circuit configured to increase a read voltage from a first read level to a second read level on the word line; and   a current sense circuit configured to, during a settling of the voltage of a bit line in response to the increase in the level of the read voltage, set the bit line of a memory cell to float after the increase in the read voltage to the second read level.   
     
     
         12 . The system of  claim 11 , wherein a duration for floating the bit line of the memory cell is predetermined. 
     
     
         13 . The system of  claim 11 , wherein the floating of the bit line results in a voltage of the bit line dropping by about 0.1 V. 
     
     
         14 . The system of  claim 11 , wherein the floating of the bit line occurs during a transition of the memory cell from a non-conductive state to a conductive state. 
     
     
         15 . The system of  claim 11 , wherein current from the current sense circuit flowing into the bit line reduces by a factor of about 10 during the floating of the bit line. 
     
     
         16 . A method comprising:
 applying, by a row decoder circuit, a second read voltage to a selected word line coupled to a set of memory cells after a first read voltage in a sequential read operation, the second read voltage higher than the first read voltage;   sinking, by a memory cell associated with the selected word line, a cell current into a source during a transition of the memory cell from a non-conductive state to a conductive state in response to the second read voltage;   pulling down a voltage of a selected bit line coupled to the memory cell in response to sinking the cell current; and   while pulling down the voltage of the selected bit line, floating the selected bit line.   
     
     
         17 . The method of  claim 16 , wherein the first read voltage corresponds to a first data state of the memory cell and the second read voltage corresponds to a second data state of the memory cell. 
     
     
         18 . The method of  claim 16 , wherein the voltage of the selected bit line floats from a fixed level to settle at a new level. 
     
     
         19 . The method of  claim 16 , wherein current flowing from a current sense circuit into the selected bit line is reduced from about 100 nanoamperes to about 10 nanoamperes. 
     
     
         20 . An apparatus, comprising:
 means for applying a read voltage to a selected word line coupled to a set of memory cells;   means for setting a selected bit line of a memory cell to float after applying the read voltage; and   means for coupling the selected bit line of the memory cell to a current flow from a current sense circuit before performing current sensing.