US2020259492A1PendingUtilityA1

Multiplexer charge injection reduction

Assignee: TEXAS INSTRUMENTS INCPriority: Aug 7, 2015Filed: Apr 28, 2020Published: Aug 13, 2020
Est. expiryAug 7, 2035(~9 yrs left)· nominal 20-yr term from priority
H03K 2217/0018H03K 17/162H03K 17/693
56
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Claims

Abstract

A multiplexer comprises: a first switch; a second switch; a dummy component coupled to the first switch and the second switch and configured to: reduce a first charge injection of the first switch, and reduce a second charge injection of the second switch; and an output coupled to the first switch, the second switch, and the dummy component. A method comprises: providing an output from either a first switch or a second switch; coupling, by a dummy component, to the first switch and the second switch; using a BBM action; and reducing, by the dummy component, a first charge injection of the first switch or a second charge injection of the second switch.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus comprising:
 a first switch comprising a first gate and a first bulk;   a first voltage supply configured to separately drive the first gate and the first bulk;   a second switch coupled to the first switch and comprising a second gate and a second bulk; and   a second voltage supply configured to separately drive the second gate and the second bulk.   
     
     
         2 . The apparatus of  claim 1 , wherein the first switch comprises a first transistor and a third transistor, wherein the first transistor comprises the first gate and the first bulk, wherein the third transistor comprises a third gate and a third bulk, and wherein the second voltage supply is further configured to separately drive the third gate and the third bulk. 
     
     
         3 . The apparatus of  claim 2 , wherein the second switch is a dummy switch. 
     
     
         4 . The apparatus of  claim 3 , wherein the second switch comprises a second transistor and a fourth transistor, wherein the second transistor comprises the second gate and the second bulk, wherein the fourth transistor comprises a fourth gate and a fourth bulk, and wherein the first voltage supply is further configured to separately drive the fourth gate and the fourth bulk.

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