Vertical cross-point memory arrays

Abstract

A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F 2 may be realized.

1 . (canceled) 
     
     
         2 . A vertical cross-point array structure comprising:
 a plurality of vertically-stacked layers of electrically conductive horizontal lines, the plurality of vertically-stacked layers of electrically conductive horizontal lines being separated by a dielectric material, and the plurality of electrically conductive horizontal lines comprising a first plurality of electrodes;   a plurality of electrically conductive vertical lines, the plurality of electrically conductive vertical lines extending through holes in the dielectric material, and the plurality of electrically conductive vertical lines comprising a second plurality of electrodes, wherein the electrically conductive vertical lines are positioned between every other horizontally-adjacent pair of the electrically conductive horizontal lines in each vertically-stacked layer of electrically conductive horizontal lines; and   an array of vertically-stacked memory elements formed between the first plurality of electrodes and the second plurality of electrodes.   
     
     
         3 . The vertical cross-point array structure of  claim 2 , wherein the holes in the dielectric material are line with one or more memory films comprising one or more resistive change memory films deposited on sidewalls of the holes. 
     
     
         4 . The vertical cross-point array structure of  claim 2 , wherein the holes in the dielectric material are line with one or more memory films comprising an insulating metal oxide (IMO) film and a conductive metal oxide (CMO) film. 
     
     
         5 . The vertical cross-point array structure of  claim 4 , wherein the IMO film has a thickness between about 5 and 50 Angstroms and the CMO film has a thickness between about 15 and 300 Angstroms. 
     
     
         6 . The The vertical cross-point array structure of  claim 2 , further comprising:
 a global bit line coupled to the array of vertically-stacked memory elements; and   a plurality of select devices to selectively couple the plurality of electrically conductive vertical lines to the global bit line.   
     
     
         7 . The vertical cross-point array structure of  claim 6 , wherein plurality of select devices are formed in a back-end of the line (BEOL) transistor layer above the array of vertically-stacked memory elements. 
     
     
         8 . The vertical cross-point array structure of  claim 2 , further comprising:
 a first set of global bit lines below the array of vertically-stacked memory elements, wherein each one of the first set of global bit lines is electrically connected to a first subset of alternate ones of the electrically conductive vertical lines.   
     
     
         9 . The vertical cross-point array structure of  claim 8 , further comprising:
 a second set of global bit lines above the array of vertically-stacked memory elements, wherein each one of the second set of global bit lines is electrically connected to a second subset of alternate ones of the electrically conductive vertical lines, wherein the first and second subsets are mutually exclusive.   
     
     
         10 . An electronic device comprising:
 a plurality of vertically-stacked layers of electrically conductive horizontal lines, the plurality of vertically-stacked layers of electrically conductive horizontal lines being separated by a dielectric material, and the plurality of electrically conductive horizontal lines comprising a first plurality of electrodes;   a plurality of electrically conductive vertical lines, the plurality of electrically conductive vertical lines extending through holes in the dielectric material, and the plurality of electrically conductive vertical lines comprising a second plurality of electrodes, wherein the electrically conductive vertical lines are positioned between every other horizontally-adjacent pair of the electrically conductive horizontal lines in each vertically-stacked layer of electrically conductive horizontal lines;   an array of vertically-stacked memory elements formed between the first plurality of electrodes and the second plurality of electrodes;   a first set of global bit lines below the array of vertically-stacked memory elements, wherein each one of the first set of global bit lines is electrically connected to a first subset of alternate ones of the electrically conductive vertical lines; and   a second set of global bit lines above the array of vertically-stacked memory elements, wherein each one of the second set of global bit lines is electrically connected to a second subset of alternate ones of the electrically conductive vertical lines, wherein the first and second subsets are mutually exclusive.   
     
     
         11 . The electronic device of  claim 10 , further comprising:
 a plurality of select devices to selectively couple the plurality of electrically conductive vertical lines to at least one of the first set of global bit lines or the second set of global bit lines, wherein plurality of select devices are formed in a back-end of the line (BEOL) transistor layer above the array of vertically-stacked memory elements.   
     
     
         12 . The electronic device of  claim 10 , wherein the holes in the dielectric material are line with one or more memory films comprising one or more resistive change memory films deposited on sidewalls of the holes. 
     
     
         13 . The electronic device of  claim 10 , wherein the holes in the dielectric material are line with one or more memory films comprising an insulating metal oxide (IMO) film and a conductive metal oxide (CMO) film. 
     
     
         14 . The electronic device of  claim 13 , wherein the IMO film has a thickness between about 5 and 50 Angstroms and the CMO film has a thickness between about 15 and 300 Angstroms. 
     
     
         15 . A memory apparatus comprising:
 a plurality of vertically-stacked layers of electrically conductive horizontal lines, the plurality of vertically-stacked layers of electrically conductive horizontal lines being separated by a dielectric material, and the plurality of electrically conductive horizontal lines comprising a first plurality of electrodes;   a plurality of electrically conductive vertical lines, the plurality of electrically conductive vertical lines extending through holes in the dielectric material, and the plurality of electrically conductive vertical lines comprising a second plurality of electrodes, wherein the holes in the dielectric material are line with one or more memory films comprising one or more resistive change memory films deposited on sidewalls of the holes, and wherein the electrically conductive vertical lines are positioned between every other horizontally-adjacent pair of the electrically conductive horizontal lines in each vertically-stacked layer of electrically conductive horizontal lines; and   an array of vertically-stacked memory elements formed between the first plurality of electrodes and the second plurality of electrodes.   
     
     
         16 . The memory apparatus of  claim 15 , wherein the holes in the dielectric material are line with one or more memory films comprising an insulating metal oxide (IMO) film and a conductive metal oxide (CMO) film. 
     
     
         17 . The memory apparatus of  claim 16 , wherein the IMO film has a thickness between about 5 and 50 Angstroms and the CMO film has a thickness between about 15 and 300 Angstroms. 
     
     
         18 . The The memory apparatus of  claim 15 , further comprising:
 a global bit line coupled to the array of vertically-stacked memory elements; and   a plurality of select devices to selectively couple the plurality of electrically conductive vertical lines to the global bit line.   
     
     
         19 . The memory apparatus of  claim 18 , wherein plurality of select devices are formed in a back-end of the line (BEOL) transistor layer above the array of vertically-stacked memory elements. 
     
     
         20 . The memory apparatus of  claim 15 , further comprising:
 a first set of global bit lines below the array of vertically-stacked memory elements, wherein each one of the first set of global bit lines is electrically connected to a first subset of alternate ones of the electrically conductive vertical lines.   
     
     
         21 . The memory apparatus of  claim 20 , further comprising:
 a second set of global bit lines above the array of vertically-stacked memory elements, wherein each one of the second set of global bit lines is electrically connected to a second subset of alternate ones of the electrically conductive vertical lines, wherein the first and second subsets are mutually exclusive.