Bit line gate structure of dynamic random access memory (dram)

Abstract

A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.

What is claimed is: 
     
         1 . A bit line gate structure of a dynamic random access memory (DRAM) , comprising:
 a polysilicon layer disposed on a substrate; and   a metal stack disposed on the polysilicon layer, wherein the maximum dopant concentration of the polysilicon layer is at an interface of the polysilicon layer and the metal stack.   
     
     
         2 . The bit line gate structure of a dynamic random access memory (DRAM) according to  claim 1 , wherein the dopant concentration of the polysilicon layer decreases gradiently from the interface of the polysilicon layer and the metal stack. 
     
     
         3 . The bit line gate structure of a dynamic random access memory (DRAM) according to  claim 1 , wherein the metal stack comprises a titanium silicon nitride layer, a tungsten silicon layer and a tungsten layer stacked from bottom to top. 
     
     
         4 . The bit line gate structure of a dynamic random access memory (DRAM) according to  claim 1 , wherein the maximum dopant concentration of the polysilicon layer is at a range of 1×10 19 /cm 3 ˜1×10 22 /cm 3 . 
     
     
         5 . The bit line gate structure of a dynamic random access memory (DRAM) according to  claim 1 , wherein the ratio of silicon to dopant of the polysilicon layer at the interface is at a range of 0.1%˜10%.