Plasma processing apparatus

Abstract

A plasma processing apparatus may include a lower electrode supporting a wafer; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring. The focus ring may include a lower region and an upper region disposed on the lower region, and the upper region increases in electrical conductivity as the upper region is closer to the lower region.

What is claimed is: 
     
         1 . A plasma processing apparatus comprising:
 a lower electrode configured to support a wafer on an upper surface of the lower electrode;   a focus ring surrounding an edge of the lower electrode and having a ring shape; and   an edge ring disposed in a position lower than a position of the focus ring,   wherein the focus ring comprises a lower region and an upper region disposed on the lower region, wherein an electrical conductivity of a first portion of the upper region is smaller than an electrical conductivity of a second portion of the upper region that is closer to the lower region than the first portion.   
     
     
         2 . The plasma processing apparatus according to  claim 1 , wherein the first portion comprises a first layer and the second portion comprises a second layer, and
 wherein the second layer is stacked on the lower region and the first layer is stacked on the second layer.   
     
     
         3 . The plasma processing apparatus according to  claim 2 , wherein the first layer and the second layer comprise a same semiconductor material, and
 wherein a dopant concentration of the second layer is larger than a dopant concentration of the first layer.   
     
     
         4 . The plasma processing apparatus according to  claim 3 , wherein the semiconductor material comprises silicon or silicon carbide. 
     
     
         5 . The plasma processing apparatus according to  claim 2 , wherein the first layer comprises a first semiconductor material and the second layer comprises a second semiconductor material different from the first semiconductor material. 
     
     
         6 . The plasma processing apparatus according to  claim 1 , wherein an electrical conductivity of the upper region gradually increases from a first side of the upper region to a second side of the upper region that is closer to the lower region than the first side. 
     
     
         7 . The plasma processing apparatus according to  claim 6 , wherein the upper region comprises a semiconductor material, and
 wherein a dopant concentration in the upper region gradually increases from the first side to the second side.   
     
     
         8 . The plasma processing apparatus according to  claim 1 , wherein an electrical conductivity of the lower region is greater than a maximum electrical conductivity of the upper region. 
     
     
         9 . The plasma processing apparatus according to  claim 1 , wherein a boundary between the lower region and the upper region is located higher than an upper surface of the lower electrode. 
     
     
         10 . The plasma processing apparatus according to  claim 1 , wherein the upper region comprises a side surface adjacent to the wafer, the side surface having a slope such that the side surface is not perpendicular to the upper surface of the lower electrode. 
     
     
         11 . A plasma processing apparatus comprising:
 a process chamber;   a lower electrode disposed in the process chamber, an upper surface of the lower electrode being configured to support a wafer;   a focus ring surrounding an upper edge of the lower electrode; and   an edge ring surrounding a lower edge of the lower electrode and supporting the focus ring,   wherein the focus ring comprises a lower region and an upper region disposed on the lower region,   wherein an electrical conductivity of a first portion of the upper region is smaller than an electrical conductivity of a second portion of the upper region that is closer to the lower region than the first portion, and   wherein the lower region has a greater electrical conductivity than a maximum electrical conductivity of the upper region.   
     
     
         12 . The plasma processing apparatus according to  claim 11 , wherein the first portion comprises a first layer stacked on the lower region and the second portion comprises a second layer stacked on the first layer. 
     
     
         13 . The plasma processing apparatus according to  claim 12 , wherein the first layer and the second layer comprise a same semiconductor material,
 wherein a dopant concentration of the second layer is larger than a dopant concentration of the first layer, and   wherein a dopant concentration of the lower region is greater than a maximum dopant concentration of the upper region.   
     
     
         14 . The plasma processing apparatus according to  claim 12 , wherein the first layer comprises a first semiconductor material and the second layer comprises a second semiconductor material different from the first semiconductor material. 
     
     
         15 . The plasma processing apparatus according to  claim 11 , wherein an electrical conductivity of the upper region gradually increases from a first side of the upper region to a second side of the upper region that is closer to the lower region than the first side. 
     
     
         16 . The plasma processing apparatus according to  claim 15 , wherein the upper region and the lower region comprise a same semiconductor material,
 wherein a dopant concentration in the upper region gradually increases from the first side to the second side, and   wherein the lower region has a greater dopant concentration than a maximum dopant concentration of the upper region.   
     
     
         17 . The plasma processing apparatus according to  claim 11 , wherein a boundary between the lower region and the upper region is located higher than the upper surface of the lower electrode, and is located lower than an upper surface of the wafer. 
     
     
         18 . A plasma processing apparatus comprising:
 a process chamber;   a lower electrode disposed in the process chamber, an upper surface of the lower electrode being configured to support a wafer;   a focus ring surrounding an upper edge of the lower electrode, the focus ring comprising a semiconductor material;   an insulation ring surrounding an outer peripheral surface of the focus ring, the insulation ring comprising an insulating material; and   an edge ring disposed in a position lower than a position of the focus ring and a position of the insulation ring,   wherein the focus ring comprises a lower region and an upper region disposed on the lower region,   wherein an electrical conductivity of a first portion of the upper region is smaller than an electrical conductivity of a second portion of the upper region that is closer to the lower region than the first portion, and   wherein the lower region has a greater electrical conductivity than a maximum electrical conductivity of the upper region.   
     
     
         19 . The plasma processing apparatus according to  claim 18 ,
 wherein the first portion comprises a first layer and the second portion comprises a second layer,   wherein the first layer and the second layer comprise a same semiconductor material, and   wherein a dopant concentration in the first layer is smaller than a dopant concentration in the second layer.   
     
     
         20 . The plasma processing apparatus according to  claim 18 , wherein an electrical conductivity of the upper region gradually increases from a first side of the upper region to a second side of the upper region that is closer to the lower region than the first side, and
 wherein a dopant concentration in the first portion is smaller than a dopant concentration in the second portion.