Multiple-state electrostatically-formed nanowire transistors

Abstract

A transistor ( 100 ), including a planar semiconducting substrate ( 36 ), a source ( 42 ) formed on the substrate, a first drain ( 102 ) formed on the substrate, and a second drain ( 104 ) formed on the substrate in a location physically separated from the first drain. At least one gate ( 38, 40 ) is formed on the substrate and is configured to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path ( 62 ) to be established within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established within the substrate from the source to the second drain.

What is claimed is: 
     
         1 . A transistor, comprising:
 a planar semiconducting substrate;   a source formed on the substrate;   a first drain formed on the substrate;   a second drain formed on the substrate in a location physically separated from the first drain; and   at least two spatially separated gates formed on the substrate and configured to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path to be established electrostatically within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established electrostatically within the substrate from the source to the second drain.   
     
     
         2 . The transistor according to  claim 1 , wherein the first and the second conductive paths are established between the two gates. 
     
     
         3 . The transistor according to  claim 1 , and comprising at least one further drain physically separated from the first and second drains and formed on the substrate, and wherein the at least two spatially separated gates are configured to selectably apply the electrical potential to the substrate in at least one further spatial pattern so as to cause at least one further conductive path to be established from the source to the at least one further drain. 
     
     
         4 . The transistor according to  claim 1 , and comprising an insulating separator formed on the substrate between the first and the second drains. 
     
     
         5 . The transistor according to  claim 1 , and comprising a non-insulating separator formed on the substrate between the first and the second drains. 
     
     
         6 . The transistor according to  claim 5 , wherein the electric potential is applied to the non-insulating separator. 
     
     
         7 . The transistor according to  claim 5 , wherein the non-insulating separator is galvanically connected to the at least one gate. 
     
     
         8 . The transistor according to  claim 1 , wherein the source, the first drain, the second drain, and the at least two spatially separated gates are formed on a single planar surface of the substrate. 
     
     
         9 . The transistor according to  claim 1 , wherein the planar semiconducting substrate has a first face and a second face opposite the first face, and wherein the source is formed on the first face; and wherein the first drain and the second drain are formed on the second face. 
     
     
         10 . The transistor according to  claim 9 , wherein the first drain and the second drain are comprised in a rectangular m×n array of physically separated drains formed on the second face, where at least one of m and n is a positive integer greater than 1. 
     
     
         11 . The transistor according to  claim 10 , wherein the at least two spatially separated gates comprise four spatially separated gates disposed about the rectangular array and formed on one of the first and second faces of the substrate. 
     
     
         12 . The transistor according to  claim 11  and comprising at least one state to gates component configured to receive a ternary input state and in response to supply respective voltage outputs to opposing two of the four gates. 
     
     
         13 . The transistor according to  claim 1 , and comprising:
 a third drain formed on the substrate, physically separated from the first and the second drain, and wherein the at least two spatially separated gates are configured to selectably apply the electrical potential to the substrate in a third spatial pattern so as to cause a third conductive path to be established within the substrate from the source to the third drain, so that the transistor performs a ternary logical operation.   
     
     
         14 . A method, comprising:
 utilizing a planar semiconducting substrate;   forming a source on the substrate;   forming a first drain on the substrate;   forming a second drain on the substrate in a location physically separated from the first drain; and   forming at least two spatially separated gates on the substrate, and configuring the at least two spatially separated gates to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path to be established electrostatically within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established electrostatically within the substrate from the source to the second drain.   
     
     
         15 . The method according to  claim 14 , wherein the first and the second conductive paths are established between the two gates. 
     
     
         16 . The method according to  claim 14 , and comprising forming at least one further drain physically separated from the first and second drains on the substrate, wherein the at least two spatially separated gates areas configured to selectably apply the electrical potential to the substrate in at least one further spatial pattern so as to cause at least one further conductive path to be established from the source to the at least one further drain. 
     
     
         17 . The method according to  claim 14 , and comprising forming an insulating separator on the substrate between the first and the second drains. 
     
     
         18 . The method according to  claim 14 , and comprising forming a non-insulating separator on the substrate between the first and the second drains. 
     
     
         19 . The method according to  claim 14 , wherein the source, the first drain, the second drain, and the at least two spatially separated gates are formed on a single planar surface of the substrate. 
     
     
         20 . The method according to  claim 14 , wherein the planar semiconducting substrate has a first face and a second face opposite the first face, and wherein the source is formed on the first face; and wherein the first drain and the second drain are formed on the second face. 
     
     
         21 . The method according to  claim 20 , wherein the first drain and the second drain are comprised in a rectangular m×n array of physically separated drains formed on the second face, where at least one of m and n is a positive integer greater than 1. 
     
     
         22 . The method according to  claim 14 , and comprising:
 forming a third drain on the substrate, physically separated from the first and the second drain, and wherein the at least two spatially separated gates are configured to selectably apply the electrical potential to the substrate in a third spatial pattern so as to cause a third conductive path to be established within the substrate from the source to the third drain, so that the transistor performs a ternary logical operation.