Packaged semiconductor assemblies and methods for manufacturing such assemblies

Abstract

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

We claim: 
     
         1 . A method of forming a semiconductor assembly, comprising:
 forming a conductive pedestal at a first bond-site of a support member, wherein the pedestal has a surface spaced apart from the support member;   attaching the support member to a die having a second bond-site;   disposing an encapsulant adjacent to the pedestal;   removing at least a portion of the encapsulant to at least partially expose the surface of the pedestal; and   forming a redistribution structure connected to the surface of the pedestal and the first bond-site and having a third bond-site between the first and second bond-sites and spaced apart from the die.   
     
     
         2 . The method of  claim 1  wherein removing at least a portion of the encapsulant comprises forming a via through the encapsulant that terminates at the surface of the pedestal. 
     
     
         3 . The method of  claim 2 , further comprising disposing a conductive member in the via and coupling the conductive member to the surface of the pedestal with the conductive member exposed for an electrical connection external to the assembly. 
     
     
         4 . A method of forming a stacked semiconductor assembly, comprising:
 singulating a first semiconductor assembly having a first die and a first bond-site at a periphery of the first assembly, the first assembly having a first footprint;   singulating a second semiconductor assembly along a singulation line, the second semiconductor assembly having a second die generally identical to the first die and a second bond-site that is at a periphery of the second assembly and is intersected by the singulation line, the second assembly having a second footprint that is smaller than the first footprint;   attaching the first assembly to the second assembly;   connecting the first bond-site to the second bond-site with an interconnect structure; and   encasing at least a portion of the interconnect structure and the bond-sites of the first and second assemblies with an encapsulant.   
     
     
         5 . The method of  claim 4  wherein attaching the first assembly to the second assembly comprises overlapping the first bond-site with the second bond-site along an axis that is generally transverse to the first and second bond-sites. 
     
     
         6 . The method of  claim 4  wherein singulating the first and second assemblies comprises dicing the first assembly with a first cutting device having a first width and dicing the second assembly with a second cutting device having a second width greater than the first width. 
     
     
         7 . The method of  claim 4  wherein singulating the first assembly comprises singulating along a singulation line that intersects the first bond-site and removing a first amount of material from the first bond-site, and wherein singulating the second assembly comprises removing a second amount of material greater than the first amount from the second bond-site. 
     
     
         8 . The method of  claim 7  wherein connecting the first bond-site with the second bond-site comprises attaching a wire bond to the first and second bond-sites. 
     
     
         9 . The method of  claim 7  wherein connecting the first bond-site with the second bond-site comprises coupling the bond-sites with a conductive ink. 
     
     
         10 . A method of manufacturing a semiconductor device, comprising:
 forming an interconnect that is connected to at least one substrate, wherein the interconnect includes a first stud bump connected to the substrate, a second stud bump connected to the substrate, and a wire connecting the first and second stud bumps;   covering the wire and the first and second stud bumps with a mold material; and   planarizing a portion of the mold material to expose a portion of the wire.   
     
     
         11 . The method of  claim 10  wherein the portion of the wire includes an exposed surface that is substantially coplanar with an outer surface of the mold material. 
     
     
         12 . The method of  claim 11  wherein:
 the interconnect is a first interconnect; 
 the surface of the wire is a first surface; and 
 the method further comprises forming a second interconnect having a second surface that directly contacts the first surface and is substantially coplanar with the first surface and the outer surface of the mold material.