Memory controller, memory module, and memory system and operation methods thereof

Abstract

A memory controller may be provided. A memory module may be provided. A memory system may be provided. A method of operating the memory system, the memory controller, or memory module may be provided. The memory system may include a memory controller and a memory module. The memory controller may provide data to the memory module to store data within the memory module. The memory controller may generate an index for storing the data. The index may be stored within the memory module

What is claimed is: 
     
         1 . The memory system, comprising:
 a plurality of data scramblers configured for generating a plurality of scrambled data by scrambling host data in different ways, respectively;   a scramble selection circuit configured for selecting one of the scrambled data as a modified data, and generating an index indicating one of the data scramblers corresponding to the selected scrambled data; and   one or more memory devices configured for storing the modified data and the index.   
     
     
         2 . The memory system of  claim 1 ,
 further comprising an error correction circuit configured for generating an error correction code (ECC) for the modified data and the index,   wherein the memory devices further store the error correction code.   
     
     
         3 . The memory system of  claim 2 , wherein the scramble selection circuit selects as the modified data the scrambled data having a greatest number of bits having a predetermined value among the scrambled data. 
     
     
         4 . The memory system of  claim 2 ,
 wherein the error correction circuit further ECC-decodes the modified data and index that are read from the memory devices using a corresponding error correction code that is read from the memory devices,   wherein the scramble selection circuit further selects one among the data scramblers according to the ECC-decoded index, and further transfers the ECC-decoded data to the selected data scrambler, and   wherein the selected data scrambler further descrambles the ECC-decoded data to restore the host data.   
     
     
         5 . The memory system of  claim 2 ,
 wherein the plurality of data scramblers, the scramble selection circuit, and the error correction circuit are included in a memory controller, and   wherein the memory devices are included in a memory module.