Circuit board and semiconductor package using the same

Abstract

A circuit board includes at least one prepreg including a fiber layer, the fiber layer being woven with a plurality of first fibers arranged in a first direction and a plurality of second fibers arranged in a second direction that is substantially perpendicular to the first direction, and a circuit layer on at least one of opposite surfaces of the at least one prepreg. The at least one prepreg has a length in the first direction greater than a length in the second direction, each of the plurality of first fibers is formed of or includes a filling yarn, and each of the plurality of second fibers is formed of or includes a warp yarn.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 at least one semiconductor chip;   a package substrate having a first surface and a second surface opposing the first surface, the first surface comprising:
 a first region on which the at least one semiconductor chip is mounted; and 
 a second region different from the first region; 
   a plurality of connection pads disposed on the first surface and wire-bonded to the at least one semiconductor chip; and   a plurality of connection terminals disposed on the second surface,   wherein the package substrate comprises:   a plurality of first fiber groups, each first fiber group comprising a filling yarn arranged in a first direction; and   a plurality of second fiber groups, each second fiber group comprising a warp yarn arranged in a second direction substantially perpendicular to the first direction, the plurality of first and second fiber groups configured to reduce non-uniformity of a coefficient of thermal expansion of the semiconductor package based on a first thermal expansion coefficient of the first region and a second thermal expansion coefficient of the second region.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the at least one semiconductor chip includes a plurality of semiconductor chips, and
 wherein the plurality of semiconductor chips are stacked on the first region in a vertical direction with respect to the first surface.   
     
     
         3 . The semiconductor package of  claim 1 , wherein the first region has a rectangular shape that is longer in the first direction than the second direction. 
     
     
         4 . The semiconductor package of  claim 1 , wherein the first thermal expansion coefficient is smaller than the second thermal expansion coefficient. 
     
     
         5 . The semiconductor package of  claim 1 , wherein a width of each of the plurality of first fiber groups is greater than a width of each of the plurality of second fiber groups. 
     
     
         6 . The semiconductor package of  claim 1 , wherein the plurality of first fiber groups and the plurality of second fiber groups are woven to have a plurality of intersection regions arranged in a matrix, and each of the plurality of intersection regions has a width in the first direction that is smaller than a length in the second direction. 
     
     
         7 . The semiconductor package of  claim 1 , wherein two adjacent first fiber groups of the plurality of first fiber groups are spaced apart from each other by a first distance and extend parallel to each other, two adjacent second fiber groups of the plurality of second fibers are spaced apart from each other by a second distance and extend parallel to each other, and the first distance is less than the second distance. 
     
     
         8 . The semiconductor package of  claim 1 , wherein the first region is surrounded by the second region. 
     
     
         9 . The semiconductor package of  claim 1 , further comprising a molding covering the at least one semiconductor chip on the first surface of the package substrate. 
     
     
         10 . The semiconductor package of  claim 1 , wherein each of the filling yarn of the plurality of first fiber groups and the warp yarn of the plurality of second fiber groups comprises a plurality of filaments, and
 wherein a number of the plurality of filaments of each of the plurality of second fiber groups is greater than a number of the plurality of filaments of each of the plurality of first fiber groups.   
     
     
         11 . The semiconductor package of  claim 1 , wherein the first surface of the package is square shape in a plan view. 
     
     
         12 . The semiconductor package of  claim 11 , wherein each edge of the square is parallel to either the first direction or the second direction. 
     
     
         13 . A semiconductor package comprising:
 two semiconductor chips arranged parallel to each other;   a package substrate having a first surface and a second surface opposing the first surface, the first surface comprising a first region in which the two semiconductor chips are mounted and a second region surrounding the first region;   a plurality of connection pads disposed on the first surface and wire-bonded to the two semiconductor chips; and   a plurality of connection terminals disposed on the second surface,   wherein the package substrate comprises:   a plurality of first fiber groups, each first fiber group comprising a filling yarn arranged in a first direction; and   a plurality of second fiber groups, each second fiber group comprising a warp yarn arranged in a second direction substantially perpendicular to the first direction, the plurality of first and second fiber groups configured to reduce non-uniformity of a coefficient of thermal expansion of the semiconductor package based on a first thermal expansion coefficient of the first region and a second thermal expansion coefficient of the second region.   
     
     
         14 . The semiconductor package of  claim 13 , wherein the two semiconductor chips are spaced apart from each other in the first direction. 
     
     
         15 . The semiconductor package of  claim 13 , wherein the two semiconductor chips have substantially the same mounting area size. 
     
     
         16 . The semiconductor package of  claim 13  wherein the first thermal expansion coefficient is smaller than the second thermal expansion coefficient. 
     
     
         17 . The semiconductor package of  claim 13 , wherein a width of each of the plurality of first fiber groups is greater than a width of each of the plurality of second fiber groups. 
     
     
         18 . The semiconductor package of  claim 13 , wherein the plurality of first fiber groups and the plurality of second fiber groups are woven to have a plurality of intersection regions arranged in a matrix, and each of the plurality of intersection regions has a width in the first direction that is smaller than a length in the second direction. 
     
     
         19 . The semiconductor package of  claim 13 , wherein two adjacent first fiber groups of the plurality of first fiber groups are spaced apart from each other by a first distance and extend parallel to each other, two adjacent second fiber groups of the plurality of second fibers are spaced apart from each other by a second distance and extend parallel to each other, and the first distance is less than the second distance. 
     
     
         20 . The semiconductor package of  claim 13 , further comprising a molding covering the two semiconductor chips on the first surface of the package substrate.