Semiconductor devices

Abstract

A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode structure including gate electrodes stacked on the substrate. The vertical channel structures extend in a first direction perpendicular to a top surface of the substrate. The gate electrodes include line regions and contact regions. The line regions extend from the main zone toward the extension zone along a second direction the second direction that is perpendicular to the first direction. The contact regions are on ends of the line regions and are thicker than the line regions. A spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a substrate including a first region and a second region;   a plurality of gate electrodes including a first gate electrode and a second gate electrode, a length of the first gate electrode being greater than a length of the second gate electrode;   a plurality of insulation patterns including a first insulation pattern and a second insulation pattern;   a plurality of channel structures disposed on the first region of the substrate, and penetrating the plurality of gate electrodes and the plurality of insulation patterns; and   a plurality of contacts including a first contact and a second contact,   wherein the first insulation pattern is disposed on the substrate,   the first gate electrode is disposed on the first insulation pattern,   the second insulation pattern is disposed on the first gate electrode,   the second gate electrode is disposed on the second insulation pattern,   the first gate electrode includes a first line region and a first contact region, the first line region being disposed on the first region of the substrate and the second region of the substrate, the first contact region being disposed on the second region of the substrate and including a first portion and a second portion disposed on the first portion,   the second gate electrode includes a second line region and a second contact region, the second line region being disposed on the first region of the substrate and the second region of the substrate, the second contact region being disposed on the second region of the substrate and including a third portion and a fourth portion disposed on the third portion,   a thickness of the first contact region is greater than a thickness of the first line region,   a thickness of the second contact region is greater than a thickness of the second line region,   an upper surface of the second portion of the first contact region is higher than an upper surface of the first line region,   an upper surface of the fourth portion of the second contact region is higher than an upper surface of the second line region,   the second contact region of the second gate electrode is vertically overlapped with the first line region of the first gate electrode,   the first contact contacts the second portion of the first contact region,   the second contact contacts the fourth portion of the second contact region,   a distal end of the second portion of the first contact region protrudes from a distal end of the first portion of the first contact region, the distal end of the first portion of the first contact region being a farthest part of the first portion from the first line region, the distal end of the second portion of the first contact region being a farthest part of the second portion from the first line region, and   a distal end of the fourth portion of the second contact region protrudes from a distal end of the third portion of the second contact region, the distal end of the third portion of the second contact region being a farthest part of the third portion from the second line region, the distal end of the fourth portion of the second contact region being a farthest part of the fourth portion from the second line region.   
     
     
         3 . The semiconductor device of  claim 2 , wherein no gate electrode is disposed directly above each of the first contact region and the second contact region. 
     
     
         4 . The semiconductor device of  claim 2 , wherein the second contact region of the second gate electrode is disposed directly above the first line region of the first gate electrode. 
     
     
         5 . The semiconductor device of  claim 2 , wherein a length of the second portion of the first contact region is greater than a length of the first portion of the first contact region, and
 a length of the fourth portion of the second contact region is greater than a length of the third portion of the second contact region.   
     
     
         6 . The semiconductor device of  claim 2 , wherein the first contact penetrates the upper surface of the second portion of the first contact region, and is inserted into the second portion of the first contact region, and
 the second contact penetrates the upper surface of the fourth portion of the second contact region, and is inserted into the fourth portion of the second contact region.   
     
     
         7 . The semiconductor device of  claim 2 , wherein a sidewall of the second portion of the first contact region is inclined, and
 a sidewall of the fourth portion of the second contact region is inclined.   
     
     
         8 . The semiconductor device of  claim 2 , wherein the thickness of the first contact region is 1.1 to 2.0 times greater than the thickness of the first line region. 
     
     
         9 . The semiconductor device of  claim 2 , wherein the plurality of insulation patterns include a third insulation pattern disposed on the second gate electrode, and
 the plurality of gate electrodes include a third gate electrode and a fourth gate electrode that are both disposed on the third insulation pattern and are spaced apart from each other.   
     
     
         10 . A semiconductor device comprising:
 a substrate including a first region and a second region;   a plurality of gate electrodes including a first gate electrode and a second gate electrode, a length of the first gate electrode being greater than a length of the second gate electrode;   a plurality of insulation patterns including a first insulation pattern and a second insulation pattern;   a plurality of channel structures disposed on the first region of the substrate, and penetrating the plurality of gate electrodes and the plurality of insulation patterns; and   a plurality of contacts including a first contact and a second contact,   wherein the first insulation pattern is disposed on the substrate,   the first gate electrode is disposed on the first insulation pattern,   the second insulation pattern is disposed on the first gate electrode,   the second gate electrode is disposed on the second insulation pattern,   the first gate electrode includes a first line region and a first contact region, the first line region being disposed on the first region of the substrate and the second region of the substrate, the first contact region being disposed on the second region of the substrate and including a first portion and a second portion disposed on the first portion,   the second gate electrode includes a second line region and a second contact region, the second line region being disposed on the first region of the substrate and the second region of the substrate, the second contact region being disposed on the second region of the substrate and including a third portion and a fourth portion disposed on the third portion,   a thickness of the first contact region is greater than a thickness of the first line region,   a thickness of the second contact region is greater than a thickness of the second line region,   an upper surface of the second portion of the first contact region is higher than an upper surface of the first line region,   an upper surface of the fourth portion of the second contact region is higher than an upper surface of the second line region,   no portion of the second gate electrode is disposed directly above the first contact region of the first gate electrode,   the first contact contacts the second portion of the first contact region,   the second contact contacts the fourth portion of the second contact region,   the upper surface of the first line region includes a first recess,   the upper surface of the second line region includes a second recess,   a distal end of the second portion of the first contact region protrudes from a distal end of the first portion of the first contact region, the distal end of the first portion of the first contact region being a farthest part of the first portion from the first line region, the distal end of the second portion of the first contact region being a farthest part of the second portion from the first line region, and   a distal end of the fourth portion of the second contact region protrudes from a distal end of the third portion of the second contact region, the distal end of the third portion of the second contact region being a farthest part of the third portion from the second line region, the distal end of the fourth portion of the second contact region being a farthest part of the fourth portion from the second line region.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the first recess is adjacent to the first contact region, and
 the second recess is adjacent to the second contact region.   
     
     
         12 . The semiconductor device of  claim 10 , wherein the second contact region of the second gate electrode is vertically overlapped with the first line region of the first gate electrode. 
     
     
         13 . The semiconductor device of  claim 10 , wherein a length of the second portion of the first contact region is greater than a length of the first portion of the first contact region, and
 a length of the fourth portion of the second contact region is greater than a length of the third portion of the second contact region.   
     
     
         14 . The semiconductor device of  claim 10 , wherein the thickness of the first contact region is 1.1 to 2.0 times greater than the thickness of the first line region, and
 the thickness of the second contact region is 1.1 to 2.0 times greater than the thickness of the second line region.   
     
     
         15 . The semiconductor device of  claim 10 , wherein a sidewall of the second portion of the first contact region is inclined. 
     
     
         16 . The semiconductor device of  claim 10 , wherein a lower portion of the first contact is inserted under the upper surface of the second portion of the first contact region. 
     
     
         17 . A semiconductor device comprising:
 a substrate including a first region and a second region;   a plurality of gate electrodes including a first gate electrode and a second gate electrode, a length of the first gate electrode being greater than a length of the second gate electrode;   a plurality of insulation patterns including a first insulation pattern and a second insulation pattern;   a plurality of channel structures disposed on the first region of the substrate, and penetrating the plurality of gate electrodes and the plurality of insulation patterns; and   a plurality of contacts including a first contact and a second contact,   wherein the first insulation pattern is disposed on the substrate,   the first gate electrode is disposed on the first insulation pattern,   the second insulation pattern is disposed on the first gate electrode,   the second gate electrode is disposed on the second insulation pattern,   the first gate electrode includes a first line region and a first contact region, the first line region being disposed on the first region of the substrate and the second region of the substrate, the first contact region being disposed on the second region of the substrate and including a first portion and a second portion disposed on the first portion,   the second gate electrode includes a second line region and a second contact region, the second line region being disposed on the first region of the substrate and the second region of the substrate, the second contact region being disposed on the second region of the substrate and including a third portion and a fourth portion disposed on the third portion,   a thickness of the first contact region is greater than a thickness of the first line region,   a thickness of the second contact region is greater than a thickness of the second line region,   an upper surface of the second portion of the first contact region is higher than an upper surface of the first line region,   an upper surface of the fourth portion of the second contact region is higher than an upper surface of the second line region,   the second contact region of the second gate electrode is not vertically overlapped with the first contact region of the first gate electrode,   the first contact contacts the second portion of the first contact region,   the second contact contacts the fourth portion of the second contact region,   a length of the second portion of the first contact region is greater than a length of the first portion of the first contact region, and   a length of the fourth portion of the second contact region is greater than a length of the third portion of the second contact region.   
     
     
         18 . The semiconductor device of  claim 17 , wherein each of the upper surface of the first line region and the upper surface of the second line region includes a recess. 
     
     
         19 . The semiconductor device of  claim 17 , wherein a distal end of the second portion of the first contact region protrudes from a distal end of the first portion of the first contact region, the distal end of the first portion of the first contact region being a farthest part of the first portion from the first line region, the distal end of the second portion of the first contact region being a farthest part of the second portion from the first line region, and
 a distal end of the fourth portion of the second contact region protrudes from a distal end of the third portion of the second contact region, the distal end of the third portion of the second contact region being a farthest part of the third portion from the second line region, the distal end of the fourth portion of the second contact region being a farthest part of the fourth portion from the second line region.   
     
     
         20 . The semiconductor device of  claim 17 , wherein a sidewall of the second portion of the first contact region is inclined. 
     
     
         21 . The semiconductor device of  claim 17 , wherein the thickness of the first contact region is 1.1 to 2.0 times greater than the thickness of the first line region.