Band-Reconfigurable and Load-Adaptive Power Amplifier

Abstract

An electronic circuit includes an input matching network, a tunable resonator, a fixed output matching network and a transistor. The tunable resonator includes a varactor and an inductor connected in series. The output matching network includes at least one shunt open-stub connected to the output of the inductor in the tunable resonator and at least one transmission line connected to the at least one shunt open-stub. The transistor includes a gate connected to the input matching network, a source connected to ground, and a drain directly connected to an input of the tunable resonator.

What is claimed: 
     
         1 . An electronic circuit comprising:
 an input matching network,   a tunable resonator comprising a varactor and an inductor connected in series to the varactor;   a fixed output matching network comprising at least one shunt open-stub connected to an output of the inductor in the tunable resonator and at least one transmission line connected to the at least one shunt open-stub, the at least one transmission line being configured to be connected to an output load,   a transistor comprising a gate connected to the input matching network, a source connected to ground, and a drain directly connected to an input of the tunable resonator.   
     
     
         2 . The electronic circuit of  claim 1 , the varactor and the inductor further comprising:
 an input in the varactor directly connected in series to the drain of the transistor and the input of the varactor being configured to be connected to a drain voltage source; and   an input of the inductor connected in series to an output of the varactor with an output of the inductor being connected in series to the input of the fixed output matching network.   
     
     
         3 . The electronic circuit of  claim 2 , wherein the transistor further comprises a gallium-arsenide p-type high-electron-mobility transistor (pHEMT). 
     
     
         4 . The electronic circuit of  claim 3 , wherein the varactor is connected to a bias voltage source that generates a bias voltage to adjust a capacitance level of the varactor between a predetermined minimum capacitance and a predetermined maximum capacitance. 
     
     
         5 . The electronic circuit of  claim 1  wherein a ratio of the predetermined maximum capacitance and the predetermined minimum capacitance of the varactor is approximately eight to one. 
     
     
         6 . The electronic circuit of  claim 1 , wherein the fixed output matching network matches an effective impedance of the output load to an impedance of the transistor at a predetermined output frequency. 
     
     
         7 . The electronic circuit of  claim 6 , wherein the predetermined output frequency is in a range of approximately 500 MHz to 3 GHz. 
     
     
         8 . The electronic circuit of  claim 1 , wherein the output signal is generated with an adjacent channel leakage ratio that is less than −35 dB. 
     
     
         9 . The electronic circuit of  claim 1  wherein the transistor further comprises a transistor selected from the list of: HBT, GaAs, CMOS, GaN, SiC, HEMT, SOI, SiGe, LDMOS, and stacked transistor variants. 
     
     
         10 . The electronic circuit of  claim 1  wherein the at least one transmission line has a first impedance and the at least one shunt open-stub has a second impedance, the first impedance being greater than the second impedance. 
     
     
         11 . The electronic circuit of  claim 1 , wherein the fixed output matching network delivers an output signal to an output load with power level in a range of approximately 0.002 watts to 5 watts. 
     
     
         12 . The electronic circuit of  claim 1  wherein the input matching network is configured to receive an input signal having a first power level and an input frequency in a range of between approximately 1 GHz and 2 GHz, the tunable resonator is tuned to the input frequency, and the electronic circuit generates an output signal from an output of the fixed output matching network having the input frequency and a second power level that is greater than the first power level. 
     
     
         13 . A method for signal amplification comprising:
 generating with an input matching network an impedance matched signal corresponding to an input signal, the impedance matched signal being provided to a gate of a transistor to control operation of the transistor;   generating with the transistor an output through a drain of the transistor that is directly connected to an input of a varactor in response to the impedance matched signal from the input matching network;   generating with the varactor and an inductor connected to an output of the varactor an amplified output signal corresponding to the input signal; and   providing the amplified output signal to a fixed output matching network comprising at least one shunt open-stub connected to an output of the inductor in the tunable resonator and at least one transmission line connected to the at least one shunt open-stub, the at least one transmission line being configured to be connected to an output load.   
     
     
         14 . The method of  claim 13 , wherein a ratio of the predetermined maximum capacitance and the predetermined minimum capacitance of the varactor is approximately eight to one.