Semiconductor Device with Stripe-Shaped Cell Trench Structures and Recessed Contacts and Method of Manufacturing Thereof

Abstract

A semiconductor device includes a plurality of first and second stripe-shaped cell trench structures formed in a semiconductor substrate and extending lengthwise in parallel with one another. Each stripe-shaped cell trench structure includes a buried electrode and an insulator layer between the buried electrode and the semiconductor substrate. A recess is formed in the insulator layer along a sidewall of one or more of the first stripe-shaped cell trench structures and vertically extends to a corresponding heavily doped contact zone. An electrically conductive material disposed in each recess contacts the corresponding buried electrode, a corresponding source zone and a corresponding heavily doped contact zone at the sidewall. Two or more of the first stripe-shaped cell trench structures are interposed between neighboring ones of the second stripe-shaped cell trench structures. Source zones alternate with portions of body zones in a lateral direction parallel to the stripe-shaped cell trench structures.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a plurality of source zones of a first conductivity type formed in a semiconductor substrate;   a plurality of body zones of a second conductivity type opposite the first conductivity type formed in the semiconductor substrate below the plurality of source zones;   a plurality of heavily doped contact zones formed in the body zones;   a plurality of first stripe-shaped cell trench structures formed in the semiconductor substrate and extending lengthwise in parallel with one another, each first stripe-shaped cell trench structure comprising a first buried electrode and a first insulator layer between the first buried electrode and the semiconductor substrate;   a plurality of second stripe-shaped cell trench structures formed in the semiconductor substrate and extending lengthwise in parallel with one another, each second stripe-shaped cell trench structure comprising a second buried electrode and a second insulator layer between the second buried electrode and the semiconductor substrate;   a recess formed in the first insulator layer along a sidewall of one or more of the first stripe-shaped cell trench structures and vertically extending to the corresponding heavily doped contact zone; and   an electrically conductive material disposed in each recess formed in the first insulator layer and contacting the corresponding first buried electrode, the corresponding source zone and the corresponding heavily doped contact zone at the sidewall,   wherein two or more of the first stripe-shaped cell trench structures are interposed between neighboring ones of the second stripe-shaped cell trench structures,   wherein the source zones alternate with portions of the body zones in a lateral direction parallel to the first and second stripe-shaped cell trench structures.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the sidewall of the one or more first stripe-shaped cell trench structures with the recess is tilted by less than 90 degrees with respect to a first main surface of the semiconductor substrate into which the plurality of first stripe-shaped cell trench structures d the plurality of second stripe-shaped cell trench structures extend. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first insulator a n width. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the width of each recess increases with increasing proximity to a first main surface of the semiconductor substrate into which the plurality of first stripe-shaped cell trench structures and the plurality of second stripe-shaped cell trench structures extend. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the width of the first buried electrode in each first stripe-shaped cell trench structure with a recessed first insulator layer decreases with increasing proximity to a first main surface of the semiconductor substrate into which the plurality of first stripe-shaped cell trench structures and the plurality of second stripe-shaped cell trench structures extend. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the width of the first buried electrode in each first stripe-shaped cell trench structure with a recessed first insulator layer is generally uniform below the recess. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising a capping layer formed on a first main surface of the semiconductor substrate into which the plurality of first stripe-shaped cell trench structures and the plurality of second stripe-shaped cell trench structures extend, wherein the electrically conductive material disposed in each recess formed in the first insulator layer extends through openings in the capping layer to form part of an overlying contact structure. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the first buried electrode of one or more of the first stripe-shaped cell trench structures is electrically contacted by the contact structure through an additional opening in the capping layer which is aligned with a top side of the first buried electrode. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the first buried electrodes are electrically coupled to a source potential, and wherein the second buried electrodes are electrically coupled to a gate potential. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the semiconductor device is an IGBT. 
     
     
         11 . The semiconductor device of  claim 1 , wherein between neighboring ones of the source zones, a body zone extends to a first main surface of the semiconductor substrate into which the plurality of first stripe-shaped cell trench structures and the plurality of second stripe-shaped cell trench structures extend. 
     
     
         12 . The semiconductor device of  claim 1 , wherein interfaces between the source zones and the body zones run approximately parallel to a first surface of the semiconductor substrate into which the plurality of first stripe-shaped cell trench structures and the plurality of second stripe-shaped cell trench structures extend at a first distance, wherein a second distance between the first surface and an edge of the electrically conductive material at a bottom of each recess formed in the first insulator layer is greater than the first distance, wherein interfaces between the body zones and a drift layer of the first conductivity type run approximately parallel to the first surface at a third distance, and wherein the second distance is smaller than the third distance. 
     
     
         13 . The semiconductor device of  claim 1 , wherein between first stripe-shaped cell trench structures of the plurality of first stripe-shaped cell trench structures for which the first buried electrode is contacted by the electrically conductive material through the recess formed in the corresponding first insulator layer, the buried electrode of at least one first stripe-shaped cell trench structure of the plurality of first stripe-shaped cell trench structures is contacted by the electrically conductive material only at a first main surface of the semiconductor substrate. 
     
     
         14 . A method of manufacturing a semiconductor device, the method comprising:
 forming a plurality of source zones of a first conductivity type in a semiconductor substrate;   forming a plurality of body zones of a second conductivity type opposite the first conductivity type in the semiconductor substrate below the plurality of source zones;   forming a plurality of heavily doped contact zones in the body zones;   forming a plurality of first stripe-shaped cell trench structures in the semiconductor substrate and extending lengthwise in parallel with one another, wherein each first cell trench structure comprises a first buried electrode and a first insulator layer between the first buried electrode and the semiconductor substrate;   forming a plurality of second stripe-shaped cell trench structures in the semiconductor substrate and extending lengthwise in parallel with one another, wherein two or more of the first stripe-shaped cell trench structures are interposed between neighboring ones of the second stripe-shaped cell trench structures, wherein each second stripe-shaped cell trench structure comprises a second buried electrode and a second insulator layer between the second buried electrode and the semiconductor substrate;   forming a recess in the first insulator layer along a sidewall of one or more of the first stripe-shaped cell trench structures and vertically extending to the corresponding heavily doped contact zone; and   disposing an electrically conductive material in each recess formed in the first insulator layer so as to contact the corresponding first buried electrode, the corresponding source zone and the corresponding heavily doped contact zone at the sidewall,   wherein the source zones alternate with portions of the body zones in a lateral direction parallel to the first and second stripe-shaped cell trench structures.   
     
     
         15 . The method of  claim 14 , wherein forming the recess in the first insulator layer along a sidewall of the one or more first stripe-shaped cell trench structures comprises tilting the sidewall of the one or more first stripe-shaped cell trench structures by less than 90 degrees with respect to a first main surface of the semiconductor substrate into which the plurality of first stripe-shaped cell trench structures and the plurality of second stripe-shaped cell trench structures extend. 
     
     
         16 . The method of  claim 15 , wherein tilting the sidewall of the one or more first stripe-shaped cell trench structures by less than 90 degrees with respect to the first main surface of the semiconductor substrate comprises removing a material of the buried first electrode at an etch selectivity with respect to a material of the semiconductor substrate of at least 5:1. 
     
     
         17 . The method of  claim 14 , wherein forming the recess in the first insulator layer along a sidewall of the one or more first stripe-shaped cell trench structures comprises decreasing the width of each recess with decreasing proximity to a first main surface of the semiconductor substrate into which the plurality of first stripe-shaped cell trench structures and the plurality of second stripe-shaped cell trench structures extend. 
     
     
         18 . The method of  claim 17 , wherein the width of the first buried electrode in each first stripe-shaped cell trench structure with a recessed first insulator layer is generally uniform below the recess. 
     
     
         19 . The method of  claim 14 , further comprising:
 forming a capping layer on a first main surface of the semiconductor substrate into which the plurality of first stripe-shaped cell trench structures and the plurality of second stripe-shaped cell trench structures extend, wherein the electrically conductive material disposed in each recess formed in the first insulator layer extends through openings in the capping layer to form part of an overlying contact structure.   
     
     
         20 . The method of  claim 19 , further comprising:
 electrically contacting the first buried electrode of one or more of the first stripe-shaped cell trench structures by the contact structure through an additional opening in the capping layer which is aligned with a top side of the first buried electrode.   
     
     
         21 . The method of  claim 14 , further comprising:
 electrically coupling the first buried electrodes to a source potential; and   electrically coupling the second buried electrodes to a gate potential.