Logic chip including embedded magnetic tunnel junctions

Abstract

An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-M RAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

1 . (canceled) 
     
     
         2 . A magnetic random access memory structure, comprising:
 a first material layer, the first material layer comprising cobalt, iron and boron;   a tunnel barrier layer on the first material layer, the tunnel barrier layer comprising magnesium and oxygen;   a second material layer on the tunnel barrier layer, the second material layer comprising cobalt, iron and boron, and the second material layer having an uppermost surface;   a third material layer above the second material layer, the third material layer comprising tantalum;   a spacer along sidewalls of the third material layer, the spacer having a bottommost surface above the uppermost surface of the second material layer.   
     
     
         3 . The magnetic random access memory structure of  claim 2 , wherein the first material layer has a first lateral width, and wherein the third material layer has a second lateral width less than the first lateral width. 
     
     
         4 . The magnetic random access memory structure of  claim 2 , wherein the first material layer has a thickness of 2.5 nanometers. 
     
     
         5 . The magnetic random access memory structure of  claim 2 , wherein the tunnel barrier layer has a thickness of 1.2 nanometers. 
     
     
         6 . The magnetic random access memory structure of  claim 2 , wherein the second material layer has a thickness of 2.5 nanometers. 
     
     
         7 . The magnetic random access memory structure of  claim 2 , wherein the third material layer has a thickness of 50 nanometers. 
     
     
         8 . The magnetic random access memory structure of  claim 2 , wherein the first and second material layers comprise Co 60 Fe 20 B 20 . 
     
     
         9 . The magnetic random access memory structure of  claim 2 , wherein the spacer comprises oxygen. 
     
     
         10 . The magnetic random access memory structure of  claim 9 , wherein the spacer comprises silicon oxide or silicon oxynitride. 
     
     
         11 . A magnetic random access memory structure, comprising:
 a bottom magnetic tunnel junction layer comprising cobalt, iron and boron;   a tunnel barrier layer on the bottom magnetic tunnel junction layer, the tunnel barrier layer comprising magnesium and oxygen;   a top magnetic tunnel junction layer on the tunnel barrier layer, the top magnetic tunnel junction layer comprising cobalt, iron and boron, the top magnetic tunnel junction layer having an uppermost surface;   a hardmask above the top magnetic tunnel junction layer, the hardmask comprising tantalum;   a spacer along sidewalls of the hardmask, the spacer having a bottommost surface above the uppermost surface of the top magnetic tunnel junction layer.   
     
     
         12 . The magnetic random access memory structure of  claim 11 , wherein the bottom magnetic tunnel junction layer has a first lateral width, and the hardmask has a second lateral width less than the first lateral width. 
     
     
         13 . The magnetic random access memory structure of  claim 11 , wherein the bottom magnetic tunnel junction layer has a thickness of 2.5 nanometers, wherein the tunnel barrier layer has a thickness of 1.2 nanometers, and wherein the top magnetic tunnel junction layer has a thickness of 2.5 nanometers. 
     
     
         14 . The magnetic random access memory structure of  claim 11 , wherein the hardmask has a thickness of 50 nanometers. 
     
     
         15 . The magnetic random access memory structure of  claim 11 , wherein the hardmask is a conductive hardmask. 
     
     
         16 . The magnetic random access memory structure of  claim 11 , wherein the bottom magnetic tunnel junction layer and the top magnetic tunnel junction layer comprise Co 60 Fe 20 B 20 . 
     
     
         17 . The magnetic random access memory structure of  claim 11 , wherein the spacer comprises oxygen. 
     
     
         18 . The magnetic random access memory structure of  claim 17 , wherein the spacer comprises silicon oxide or silicon oxynitride. 
     
     
         19 . A system, comprising:
 a processor; and   a memory coupled to the processor, the memory comprising a magnetic random access memory structure, the magnetic random access memory structure comprising:
 a first material layer, the first material layer comprising cobalt, iron and boron; 
 a tunnel barrier layer on the first material layer, the tunnel barrier layer comprising magnesium and oxygen; 
 a second material layer on the tunnel barrier layer, the second material layer comprising cobalt, iron and boron, and the second material layer having an uppermost surface; 
 a third material layer above the second material layer, the third material layer comprising tantalum; 
   a spacer along sidewalls of the third material layer, the spacer having a bottommost surface above the uppermost surface of the second material layer.   
     
     
         20 . The system of  claim 19 , further comprising:
 a chipset, wherein the processor is coupled to the chipset.   
     
     
         21 . The system of  claim 19 , wherein the system is a communication device selected from the group consisting of a cell phone, a Smartphone, a netbook, a notebook, a personal computer, a watch and a camera.