Methods related to managing parasitic capacitance and voltage handling of stacked radio frequency devices

Abstract

Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. A method can include providing a stack in a radio frequency switch arrangement, the stack arranged in relation to a ground plane, the stack including a plurality of switching elements coupled in series with one another, the stack having first and second ends, the first end including a respective terminal of a first one of the plurality of switching elements. The method can also include forming a first solder bump coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement.

What is claimed is: 
     
         1 . A method of managing a parasitic capacitance of a radio frequency switch arrangement, comprising:
 providing a stack in a radio frequency switch arrangement, the stack arranged in relation to a ground plane, the stack including a plurality of switching elements coupled in series with one another, the stack having first and second ends, the first end including a respective terminal of a first one of the plurality of switching elements; and   forming a first solder bump coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement.