Method for forming a semiconductor device structure and related semiconductor device structures

Abstract

A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.

What is claimed is: 
     
         1 . A semiconductor device structure comprising:
 a PMOS gate electrode disposed over a PMOS gate dielectric, wherein the PMOS gate electrode comprises a metal nitride film disposed directly over the PMOS gate dielectric and a molybdenum film disposed directly over the metal nitride film.   
     
     
         2 . The semiconductor device structure of  claim 1 , wherein the metal nitride film comprises at least one of titanium nitride, tantalum nitride, or niobium nitride. 
     
     
         3 . The semiconductor device structure of  claim 1 , wherein the PMOS gate electrode has an effective work function of greater than 5 eV. 
     
     
         4 . The semiconductor device structure of  claim 1 , wherein the metal nitride film has a thickness of less than 30 Angstroms. 
     
     
         5 . The semiconductor device structure of  claim 1 , wherein the molybdenum film has a thickness of less than 300 nanometers. 
     
     
         6 . The semiconductor device structure of  claim 1 , wherein the PMOS gate dielectric comprises at least one of hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), hafnium silicate (HfSiO x ) and lanthanum oxide (La 2 O 3 ). 
     
     
         7 . The semiconductor device structure of  claim 1 , wherein the molybdenum film comprises a gate fill metal, the gate fill metal being disposed in and filling a gate trench. 
     
     
         8 . The semiconductor device structure of  claim 1 , wherein the metal nitride film has a thickness between approximately 5 Angstroms and approximately 30 Angstroms. 
     
     
         9 . A semiconductor device structure comprising:
 a NMOS gate electrode disposed over a NMOS gate dielectric, wherein the NMOS gate electrode comprises a metal nitride film disposed directly over the NMOS gate dielectric, a first work function metal disposed directly over the metal nitride film, an additional metal nitride film disposed over the first work function metal and a molybdenum film disposed over the additional metal nitride film.   
     
     
         10 . A semiconductor device structure of  claim 9 , wherein the metal nitride film comprises at least one of titanium nitride, tantalum nitride, or niobium nitride. 
     
     
         11 . A semiconductor device structure of  claim 9 , wherein the additional metal nitride film comprises at least one of titanium nitride, tantalum nitride, or niobium nitride. 
     
     
         12 . The semiconductor device structure of  claim 9 , wherein the NMOS gate electrode has an effective work function of greater than 4.2 eV. 
     
     
         13 . The semiconductor device structure of  claim 9 , wherein the metal nitride film has a thickness of less than 30 Angstroms. 
     
     
         14 . The semiconductor device structure of  claim 9 , wherein the first work function metal comprises a metal carbide. 
     
     
         15 . The semiconductor device structure of  claim 9 , wherein the metal carbide comprises at least one of titanium carbide, tantalum carbide, titanium aluminum carbide, or niobium aluminum carbide. 
     
     
         16 . The semiconductor device structure of  claim 9 , wherein the first work function metal has a thickness of less than 3 nanometers. 
     
     
         17 . The semiconductor device structure of  claim 9 , wherein the additional metal nitride film has a thickness of less than 3 nanometers. 
     
     
         18 . The semiconductor device structure of  claim 9 , wherein the molybdenum film has a thickness of less than 300 nanometers. 
     
     
         19 . The semiconductor device structure of  claim 9 , wherein the molybdenum film comprises a gate fill metal, the gate fill metal being disposed in and filling a gate trench. 
     
     
         20 . A complementary metal-oxide-semiconductor (CMOS) device structure comprising:
 a PMOS gate electrode disposed over a PMOS gate dielectric, wherein the PMOS gate electrode comprises a first titanium nitride film disposed directly over the PMOS gate dielectric and a molybdenum film disposed directly over the first titanium nitride film; and   a NMOS gate electrode disposed over a NMOS gate dielectric, wherein the NMOS gate electrode comprises a second titanium nitride film disposed directly over the NMOS gate dielectric, a first work function metal disposed directly over the second titanium nitride film, a third titanium nitride film disposed over the first work function metal and a molybdenum film disposed over the third titanium nitride film.