Method and apparatus for performing profile guided optimization for high-level synthesis

Abstract

A method for designing a system on a target device includes performing a high-level compilation of a computer program language description of the system to generate a hardware description language (HDL) of the system. The high-level compilation performs optimizations in response to profile data obtained from an earlier compilation of the system.

1 - 25 . (canceled) 
     
     
         26 . A method, comprising:
 providing a development environment, wherein the development environment is configured to enable optimization of a field programmable gate array (FPGA) configured to implement a system;   directing, by the development environment, a compilation of the system defined using one or more kernels into hardware logic for the system;   generating, by the development environment, a high-level synthesis report comprising performance estimates and utilization estimates of the system based on results from the compilation;   accessing, by the development environment, profiling data generated based on the system; and   providing, by the development environment, optimization guidance based at least in part on the high-level synthesis report and on the profiling data wherein the optimization guidance provides a recommendation for changing at least a portion of the one or more kernels when optimizing the system.   
     
     
         27 . The method of  claim 26 , comprising using one or more counters to determine at least a portion of the profiling data. 
     
     
         28 . The method of  claim 26 , wherein the profiling data comprises timing information associated with the system. 
     
     
         29 . The method of  claim 26 , wherein the high-level synthesis report comprises timing and latency information for the system. 
     
     
         30 . The method of  claim 26 , comprising directing, by the development environment, an optimization of the system after providing the recommendation. 
     
     
         31 . The method of  claim 26 , comprising:
 directing, by the development environment, one or more kernel optimizations based on the optimization guidance.   
     
     
         32 . The method of  claim 31 , wherein the one or more kernel optimizations comprise an unrolling of a loop of the system. 
     
     
         33 . The method of  claim 31 , wherein the one or more kernel optimizations comprise pipelining functions. 
     
     
         34 . The method of  claim 26 , wherein the optimization guidance is associated with paths through one or more FPGA resources for the one or more kernels, a frequency of the system for the one or more kernels, or a latency of the system for the one or more kernels, or any combination thereof. 
     
     
         35 . The method of  claim 26 , comprising directing, by the development environment, generation of a bit stream configured to implement the system into a target device. 
     
     
         36 . The method of  claim 26 , wherein the profiling data is generated from a simulation of the system. 
     
     
         37 . The method of  claim 26 , wherein the profiling data is generated from a runtime execution of the system. 
     
     
         38 . A system, comprising:
 a field programmable gate array (FPGA) development environment configured to be stored on a non-transitory, programmable computer-readable medium, wherein when executed by a processing device, the FPGA development environment causes the processing device to perform operations comprising:
 directing a compilation of a computing language description of a system to generate hardware logic for the system corresponding to a first FPGA design; 
 generating a high-level synthesis report comprising performance estimates and utilization estimates of the first FPGA design based on results from the compilation; 
 generating a design recommendation based at least in part on the high-level synthesis report and profiling data generated based at least in part on the system; and 
 presenting the design recommendation on a graphical user interface indicating an adjustment to a portion of the first FPGA design to generate a second FPGA design. 
   
     
     
         39 . The system of  claim 38 , comprising an FPGA configured to be programmed with the second FPGA design. 
     
     
         40 . The system of  claim 39 , wherein the operations comprise programming the FPGA with the second FPGA design. 
     
     
         41 . The system of  claim 38 , wherein the high-level synthesis report comprises a value associated with an area used to implement the first FPGA design in an FPGA 
     
     
         42 . The system of  claim 38 , wherein the high-level synthesis report comprises information associated with an estimate of implementing the first FPGA design in an FPGA. 
     
     
         43 . The system of  claim 38 , wherein the second FPGA design is characterized by a timing delay less than that of the first FPGA design. 
     
     
         44 . A method, comprising:
 directing a compilation of a computing language description of a first field programmable gate array (FPGA) design to generate hardware logic to be used to implement the first FPGA design in a system;   accessing a high-level synthesis report comprising performance estimates and utilization estimates of the first FPGA design based on results from the compilation;   accessing profiling data generated based at least in part on the system;   generating a design recommendation based at least in part on the high-level synthesis report and the profiling data; and   presenting the design recommendation on a graphical user interface indicating an adjustment to a portion of the first FPGA design to generate a second FPGA design.   
     
     
         45 . The method of  claim 44 , wherein generating the design recommendation comprises generating the design recommendation based at least in part on timing information associated with the compilation and indicated by the profiling data. 
     
     
         46 . The method of  claim 44 , wherein generating the design recommendation comprises recommending an unrolling of a loop associated with the first FPGA design. 
     
     
         47 . The method of  claim 44 , wherein computing language description of the system corresponds to an OpenCL kernel description of the system.