Approximating Functions

Abstract

A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h−1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.

What is claimed is: 
     
         1 . A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment extending between a pair of break points and having a gradient and a base value, the binary logic circuit comprising:
 a plurality of logic chains each comprising:
 a binary multiplier configured to perform multiplication by a gradient, and 
 a binary adder configured to add a base value to an input or output of the binary multiplier; 
   wherein each of the gradients and each of the break points has a minimum extended Hamming weight which is less than or equal to a threshold value.   
     
     
         2 . The binary logic circuit of  claim 1 , wherein the binary logic circuit further comprises selection logic configured to select one of the logic chains in dependence on an input variable so as to provide, for the input variable, an approximate value of the mathematical function. 
     
     
         3 . The binary logic circuit of  claim 2 , wherein the binary logic circuit further comprises an input for receiving the input variable in the predefined range. 
     
     
         4 . The binary logic circuit of  claim 1 , wherein each of the plurality of logic chains is operable to provide an approximate value of the mathematical function over part of the predefined range. 
     
     
         5 . The binary logic circuit of  claim 1 , wherein each linear segment has one of a predetermined set of fixed gradients, and wherein each of the fixed gradients in the predetermined set of fixed gradients has a respective minimum extended Hamming weight which is less than or equal to the threshold value. 
     
     
         6 . The binary logic circuit of  claim 5 , wherein the extended minimum Hamming weights of the respective fixed gradients of the predetermined set are less than or equal to 3. 
     
     
         7 . The binary logic circuit of  claim 1 , wherein the binary multiplier is configured to perform multiplication by a gradient using a number of binary adders, wherein said number of binary adders is one less than the minimum extended Hamming weight for the respective gradient. 
     
     
         8 . The binary logic circuit of  claim 1 , wherein the threshold value is 2 or 3. 
     
     
         9 . The binary logic circuit of  claim 2 , wherein each linear segment extends between a pair of break points, and wherein the selection logic is configured to select one of the logic chains by comparing the input variable to a predetermined set of break values associated with the break points, each break value representing a value of the input variable delimiting one or more linear segments. 
     
     
         10 . The binary logic circuit of  claim 9 , the selection logic being configured to determine the pair of adjacent break values between which the input variable lies and, responsive to that determination, select the logic chain corresponding to the linear segment lying between that pair of adjacent break values. 
     
     
         11 . The binary logic circuit of  claim 9 , wherein each of the break values has a minimum extended Hamming weight which is less than or equal to a further threshold value, and wherein each of the set of break values is used in the selection logic in the form of a representation of that break value having a minimum extended Hamming weight for that break value. 
     
     
         12 . The binary logic circuit of  claim 11 , wherein the minimum extended Hamming weight of each of the set of break values is less than or equal to 3. 
     
     
         13 . The binary logic circuit of  claim 1 , wherein the mathematical function is expressed in the form y=f(x), where x and y represent values along respective Cartesian axes, and wherein the binary adder of each logic chain is arranged to add the respective base value to the output of the binary multiplier. 
     
     
         14 . The binary logic circuit of  claim 13 , wherein each linear segment represents part of a line that crosses the y axis at the base value. 
     
     
         15 . The binary logic circuit of  claim 2 , wherein the mathematical function is expressed in the form y=f(x), where x and y represent values along respective Cartesian axes, and wherein the binary adder of each logic chain is arranged to add the respective base value to the input variable. 
     
     
         16 . The binary logic circuit of  claim 15 , wherein each linear segment represents part of a line that crosses the x axis at the base value. 
     
     
         17 . The binary logic circuit of  claim 1 , wherein the mathematical function is a continuous smooth function over the predefined range, or wherein the mathematical function is a base 2 logarithm and the predefined range is between 1 and 2, or wherein the mathematical function is a gamma function and the predefined range is between 0 and 1. 
     
     
         18 . The binary logic circuit of  claim 1 , wherein at least one of the plurality of logic chains comprises a binary multiplier configured to perform multiplication by a fixed gradient having a minimum extended Hamming weight of greater than one. 
     
     
         19 . A method of deriving a hardware representation of a binary logic circuit configured to approximate a mathematical function over a predefined range as a series of linear segments, the method comprising:
 fitting a plurality of linear segments to the function over the predefined range, each linear segment extending between a pair of break points and having a gradient and a base value; and   deriving a hardware representation for a binary logic circuit which comprises:
 for each of the plurality of linear segments:
 a binary multiplier configured to perform multiplication by the gradient of the segment, and 
 a binary adder configured to add the base value for the segment to an input or output of the binary multiplier; 
 
   wherein each of the gradients and each of the break points has a minimum extended Hamming weight which is less than or equal to a threshold value.   
     
     
         20 . A method of manufacturing a binary logic circuit in accordance with a hardware representation derived using a method configured to approximate a mathematical function over a predefined range as a series of linear segments, comprising the steps of:
 fitting a plurality of linear segments to the function over the predefined range, each linear segment extending between a pair of break points and having a gradient and a base value;   deriving a hardware representation for a binary logic circuit which comprises:
 for each of the plurality of linear segments:
 a binary multiplier configured to perform multiplication by the gradient of the segment, and 
 a binary adder configured to add the base value for the segment to an input or output of the binary multiplier; 
 
   wherein each of the gradients and each of the break points has a minimum extended Hamming weight which is less than or equal to a threshold value; and   using the derived hardware representation to manufacture the binary logic circuit.