Memory buffers and modules supporting dynamic point-to-point connections

Abstract

A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.

1 . (canceled) 
     
     
         2 . A memory controller integrated circuit (IC) device that controls memory devices via a buffer device, the memory devices including first and second sets of memory devices disposed on a memory module, the memory controller IC device comprising:
 a circuit to receive configuration information from serial presence detect (SPD) logic of the memory module during a power-on process;   a command interface to issue an instruction to the buffer device, along with a value representative of a module data width selected from one of a first data-width mode and a second data-width mode, the instruction indicating to the buffer device to load the value representative of the module data width into a register on the buffer device, wherein the value is based on the configuration information;   wherein during a normal operation subsequent to the power-on process:   the command interface to issue via the buffer device:
 read commands to both the first and second sets of memory devices during operation in a first data-width mode; and 
 read commands to a selected one of the first and second sets of memory devices in a second data-width mode; and 
   a data interface to receive read data from the memory devices via the buffer device, the data interface:
 using a first width in the first data-width mode, the memory controller IC device to receive, via the buffer device, the read data in parallel from both the first and second sets of memory devices; and 
 using a second width in the second data-width mode, the memory controller IC device to receive, via the buffer device, the read data in parallel from the selected one of the first and second sets of memory devices. 
   
     
     
         3 . The memory controller IC device of  claim 2 , wherein the command interface is of a command-interface width in the first data-width mode and of the same command-interface width in the second data-width mode. 
     
     
         4 . The memory controller IC device of  claim 3 , the command interface to further issue memory addresses to the buffer device. 
     
     
         5 . The memory controller IC device of  claim 2 , wherein the first data-width mode communicates the data at twice the data width of the second data-width mode. 
     
     
         6 . The memory controller IC device of  claim 2 , the memory controller to detect a number of modules, including the memory module, and load the register responsive to the detected number of modules. 
     
     
         7 . The memory controller IC device of  claim 2 , wherein the power-on process comprises a self-test of the memory controller IC device and the memory devices. 
     
     
         8 . The memory controller IC device of  claim 2 , wherein the SPD logic comprises an IC separate from the buffer device. 
     
     
         9 . The memory controller IC device of  claim 2 , wherein the SPD logic is integrated into the buffer device. 
     
     
         10 . The memory controller IC device of  claim 2 , wherein the first set of the memory devices is of a first rank group and the second set of the memory devices is of a second rank group, the buffer device directing commands to both of the first rank group and the second rank group in the first data width and directing commands to only one of the first rank group and the second rank group in the second data width. 
     
     
         11 . A method of operation in a memory controller integrated circuit (IC) device that controls memory devices via a memory buffer, the memory devices including first and second sets of memory devices disposed on a memory module, the method comprising:
 during a power-on process, reading configuration information from serial presence detect (SPD) logic of the memory module;   issuing an instruction to the buffer device, along with a value representative of a module data width selected from one of a first data width and a second data width, the instruction indicating to the buffer device to load the value representative of the module data width into a register on the buffer device, wherein the value representative of the module data width is based on the configuration information;   wherein during a normal operation of the memory module subsequent to the power up process:
 for a first data width, the memory controller IC device issuing commands to both first and second sets of memory devices, to receive data in parallel from both the first and second sets of memory devices via the buffer device; and 
 for a second data width, the memory controller IC device issuing commands to a selected one of the first and second sets of memory devices, to receive respective data in parallel from the selected one of the first and second sets of memory devices via the buffer device. 
   
     
     
         12 . The method of  claim 11 , wherein the instruction is of an instruction width for the first data width and the instruction is of the instruction width in for the second data width. 
     
     
         13 . The method of  claim 11 , further comprising issuing memory addresses to the buffer device. 
     
     
         14 . The method of  claim 11 , wherein the first data width is twice the second data width. 
     
     
         15 . The method of  claim 11 , further comprising detecting a number of modules, including the memory module, and loading the register responsive to the detected number of modules. 
     
     
         16 . The method of  claim 11 , further comprising executing a self-test operation of the memory devices during the power on process. 
     
     
         17 . The method of  claim 11 , wherein the SPD logic comprises an IC separate from the buffer device. 
     
     
         18 . The method of  claim 11 , wherein the SPD logic is integrated into the buffer device. 
     
     
         19 . The method of  claim 11 , wherein the first set of the memory devices is of a first rank group and the second set of the memory devices is of a second rank group, the method further comprising directing commands to both of the first rank group and the second rank group in the first data width and directing commands to only one of the first rank group and the second rank group in the second data width. 
     
     
         20 . A memory controller integrated circuit (IC) device that controls memory devices via a buffer device, the memory devices including first and second ranks of memory devices disposed on a memory module, the IC device comprising:
 a circuit to receive configuration information from serial presence detect (SPD) logic of the memory module;   a command interface to issue an instruction to the buffer device, along with a value representative of a module data width selected from one of a first data width and a second data width, the instruction indicating to the buffer device to load the value representative of the module data width into a register on the buffer device, wherein the value representative of the module data width is based on the configuration information, wherein:
 for the first data width, the command interface is to issue commands to both first and second ranks of memory devices; and 
 for a second data width, the command interface is to issue commands to a selected one of the first and second ranks of memory devices; 
   and   a data interface configured as the first data width to receive data in parallel from both the first and second ranks of memory devices via the buffer device, and configured as the second data width to receive respective data in parallel from the selected one of the first and second ranks of memory devices via the buffer device.