Management of Processor Performance Based on User Interrupts

Abstract

In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.

What is claimed is: 
     
         1 . A method comprising:
 creating, by a processor, a task structure including a user posted interrupt descriptor associated with a user interrupt, the user posted interrupt descriptor including at least one field to indicate whether to adjust a performance state of a destination processing engine based on user interrupt notifications; and   responsive to a receipt of a user interrupt notification, adjusting the performance state of the destination processing engine based on the at least one field of the user posted interrupt descriptor.   
     
     
         2 . The method of  claim 1 , wherein the at least one field of the user posted interrupt descriptor includes a global setting field to indicate that the performance state of the destination processing engine is adjusted in response to any user vector in the user interrupt notification. 
     
     
         3 . The method of  claim 2 , wherein the global setting field comprises a single bit that indicates that the performance state of the destination processing engine is increased in response to any user vector in the user interrupt notification. 
     
     
         4 . The method of  claim 2 , wherein the at least one field of the user posted interrupt descriptor includes a vector settings field to indicate that the performance state of the destination processing engine is adjusted in response to a specified set of user vectors in the user interrupt notification. 
     
     
         5 . The method of  claim 4 , wherein the vector settings field comprises a plurality of bits to identify one or more user vectors that, when indicated in the user interrupt notification, cause the performance state of the destination processing engine to be increased. 
     
     
         6 . The method of  claim 4 , comprising ignoring the vector settings field in response to a determination that the global setting field is set to indicate that the performance state of the destination processing engine is increased in response to any user vector in the user interrupt notification. 
     
     
         7 . The method of  claim 1 , comprising comparing a user vector in the user interrupt notification to the at least one field of the user posted interrupt descriptor to determine whether to adjust the performance state of the destination processing engine. 
     
     
         8 . The method of  claim 1 , wherein the user posted interrupt descriptor also includes at least one of an outstanding notification field that indicates whether any user interrupt notification is outstanding and a suppress notification field that indicates whether to send a notification when posting a user interrupt. 
     
     
         9 . An apparatus comprising:
 a plurality of processing engines; and   processing logic to:
 generate a task structure including a user posted interrupt descriptor associated with a user interrupt, the user posted interrupt descriptor including at least one field to indicate whether to adjust a performance state of a destination processing engine based on user interrupt notifications; and 
 responsive to a receipt of a user interrupt notification, adjust the performance state of the destination processing engine based on the at least one field of the user posted interrupt descriptor. 
   
     
     
         10 . The apparatus of  claim 9 , wherein the at least one field of the user posted interrupt descriptor includes a global setting field to indicate that the performance state of the destination processing engine is adjusted in response to any user vector in the user interrupt notification. 
     
     
         11 . The apparatus of  claim 10 , wherein the global setting field comprises a single bit that indicates that the performance state of the destination processing engine is increased in response to any user vector in the user interrupt notification. 
     
     
         12 . The apparatus of  claim 10 , wherein the at least one field of the user posted interrupt descriptor includes a vector settings field to indicate that the performance state of the destination processing engine is adjusted in response to a specified set of user vectors in the user interrupt notification. 
     
     
         13 . The apparatus of  claim 12 , wherein the vector settings field comprises a plurality of bits to identify one or more user vectors that, when indicated in the user interrupt notification, cause the performance state of the destination processing engine to be increased. 
     
     
         14 . The apparatus of  claim 12 , the processing logic to ignore the vector settings field in response to a determination that the global setting field is set to indicate that the performance state of the destination processing engine is increased in response to any user vector in the user interrupt notification. 
     
     
         15 . The apparatus of  claim 9 , the processing logic to compare a user vector in the user interrupt notification to the at least one field of the user posted interrupt descriptor to determine whether to adjust the performance state of the destination processing engine. 
     
     
         16 . A system comprising:
 a processor comprising a plurality of processing engines and logic to:
 generate a task structure including a user posted interrupt descriptor associated with a user interrupt, the user posted interrupt descriptor including at least one field to indicate whether to adjust a performance state of a destination processing engine based on user interrupt notifications; and 
 responsive to a receipt of a user interrupt notification, adjust the performance state of the destination processing engine based on the at least one field of the user posted interrupt descriptor: and 
   a system memory coupled to the processor.   
     
     
         17 . The system of  claim 16 , wherein the at least one field of the user posted interrupt descriptor includes a global setting field to indicate that the performance state of the destination processing engine is adjusted in response to any user vector in the user interrupt notification. 
     
     
         18 . The system of  claim 17 , wherein the global setting field comprises a single bit that indicates that the performance state of the destination processing engine is increased in response to any user vector in the user interrupt notification. 
     
     
         19 . The system of  claim 17 , wherein the at least one field of the user posted interrupt descriptor includes a vector settings field to indicate that the performance state of the destination processing engine is adjusted in response to a specified set of user vectors in the user interrupt notification. 
     
     
         20 . The system of  claim 19 , wherein the vector settings field comprises a plurality of bits to identify one or more user vectors that, when indicated in the user interrupt notification, cause the performance state of the destination processing engine to be increased. 
     
     
         21 . The system of  claim 19 , the logic to ignore the vector settings field in response to a determination that the global setting field is set to indicate that the performance state of the destination processing engine is increased in response to any user vector in the user interrupt notification.