Semiconductor device, semiconductor system, and system

Abstract

A semiconductor device, semiconductor system, and system may be provided. The semiconductor system may include one semiconductor device of a first semiconductor device and a second semiconductor device suitable for transmitting and receiving addresses and encrypted data. The one semiconductor device may include an address output circuit configured to output the addresses. The one semiconductor device may include an encryption circuit configured to output the encrypted data based on normal data and the addresses. The one semiconductor device may include a decryption circuit configured to output the normal data based on the addresses and the encrypted data.

What is claimed is: 
     
         1 . A semiconductor system including a controller comprising:
 an address output circuit configured to provide addresses to a memory device;   an encryption circuit configured to generate encrypted data based on normal data and mapping addresses, and output the encrypted data to the memory device;   a decryption circuit configured to generate the normal data based on the encrypted data provided from the memory device and the mapping addresses; and   an encryption control circuit configured to generate the mapping addresses based on a control signal and the addresses.   
     
     
         2 . The semiconductor system according to  claim 1 , further comprising:
 a control signal output circuit including a register configured for providing the control signal.   
     
     
         3 . The semiconductor system according to  claim 1 , wherein the encryption circuit performs a logic operation with the normal data and the mapping addresses, and outputs the encrypted data. 
     
     
         4 . The semiconductor system according to  claim 3 , wherein the encryption circuit comprises a plurality of logic combining circuits which logically combine the normal data and the mapping addresses. 
     
     
         5 . The semiconductor system according to  claim 4 , wherein each logic combining circuit outputs encrypted data of a first level when normal data and a mapping address are the same level, and outputs encrypted data of a second level when normal data and a mapping address are different levels. 
     
     
         6 . The semiconductor system according to  claim 1 , wherein the decryption circuit performs a logic operation with the encrypted data and the mapping addresses, and outputs the normal data. 
     
     
         7 . The semiconductor system according to  claim 6 , wherein the decryption circuit comprises a plurality of logic combining circuits which logically combine the encrypted data and the mapping addresses. 
     
     
         8 . The semiconductor system according to  claim 7 , wherein each logic combining circuit outputs normal data of a first level when encrypted data and a mapping address are the same level, and outputs normal data of a second level when encrypted data and a mapping address are different levels. 
     
     
         9 . The semiconductor system according to  claim 1 ,
 wherein the addresses include a first address and a second address,   wherein the mapping addresses include a first mapping address and a second mapping address, and   wherein the encryption control circuit outputs the second address as the second mapping address when the first address is outputted as the first mapping address based on the control signal or outputs the second address as the first mapping address when the first address is outputted as the second mapping address based on the control signal.   
     
     
         10 . The semiconductor system according to  claim 9 ,
 wherein the encryption control circuit comprises a plurality of selective output circuits, and   wherein the plurality of selective output circuits output the addresses as the mapping addresses based on the control signal.   
     
     
         11 . The semiconductor system according to  claim 10 , wherein each selective output circuit is configured to perform an operation of a demultiplexer.