Method of making heteroepitaxial structures and device formed by the method

Abstract

A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

What is claimed is: 
     
         1 . A method for making a heteroepitaxial layer, the method comprising:
 providing a semiconductor substrate;   forming a nanostructured pedestal on the semiconductor substrate, the pedestal having a top surface and a side surface;   providing a selective growth mask layer on the top surface and side surface of the pedestal;   removing a portion of the selective growth mask layer to expose the top surface of the pedestal;   selectively etching-back the exposed top surface of the pedestal to form a seed area, the seed area having a linear surface dimension that ranges from about 10 nm to about 100 nm; and   growing the heteroepitaxial layer on the seed area, wherein the heteroepitaxial layer is substantially unrestricted by sidewalls during growth.   
     
     
         2 . The method of  claim 1 , wherein the exposed top surface is etched back such that it forms a seed area that is approximately coplanar with a top surface of the selective growth mask layer. 
     
     
         3 . The method of  claim 1 , wherein the heteroepitaxial layer is substantially defect-free. 
     
     
         4 . The method of  claim 1 , wherein an interface between the heteroepitaxial layer and the seed area is substantially defect-free. 
     
     
         5 . The method of  claim 1 , wherein a portion of the heteroepitaxial layer above the selective growth mask layer has a rhombic cross-sectional shape. 
     
     
         6 . The method of  claim 1 , wherein the heteroepitaxial layer slopes outward proximate the seed area. 
     
     
         7 . The method of  claim 1 , wherein the heteroepitaxial layer slopes inward distal from the seed area. 
     
     
         8 . The method of  claim 1 , wherein the entire heteroepitaxial layer is grown entirely above a top surface of the selective growth mask layer. 
     
     
         9 . The method of  claim 1 , wherein the semiconductor substrate is comprised of silicon. 
     
     
         10 . The method of  claim 1 , wherein the semiconductor substrate comprises silicon having a [001] direction normal to the substrate surface. 
     
     
         11 . The method of  claim 10 , wherein removing the portion of the selective growth mask layer to expose the seed area comprises etching the insulator to expose a (001) plane of the silicon material. 
     
     
         12 . The method of  claim 1 , wherein a second linear surface dimension ranges from about 200 nm to about 5000 nm. 
     
     
         13 . The method of  claim 1 , wherein the selective growth mask layer is comprised of silicon dioxide. 
     
     
         14 . The method of  claim 1 , further comprising forming a portion of a transistor from the heteroepitaxial layer. 
     
     
         15 . The method of  claim 1 , the seed area having a linear surface dimension that ranges from about 10 nm to about 50 nm. 
     
     
         16 . A method for making a heteroepitaxial layer, the method comprising:
 providing a semiconductor substrate;   forming a nanostructured pedestal on the semiconductor substrate, the pedestal having a top surface and a side surface;   providing a selective growth mask layer on the top surface and side surface of the pedestal;   removing a portion of the selective growth mask layer to expose the top surface of the pedestal;   selectively etching-back the exposed top surface of the pedestal to form a seed area, the seed area having a linear surface dimension that ranges from about 10 nm to about 100 nm, wherein the seed area is substantially level with the remaining selective growth mask layer; and   growing the heteroepitaxial layer on the seed area.   
     
     
         17 . The method of  claim 16 , wherein the heteroepitaxial layer is substantially unrestricted by sidewalls during growth. 
     
     
         18 . The method of  claim 16 , wherein the heteroepitaxial layer is substantially defect-free. 
     
     
         19 . The method of  claim 16 , wherein an interface between the heteroepitaxial layer and the seed area is substantially defect-free. 
     
     
         20 . The method of  claim 16 , wherein a portion of the heteroepitaxial layer above the selective growth mask layer has a rhombic cross-sectional shape. 
     
     
         21 . The method of  claim 16 , wherein the heteroepitaxial layer slopes outwardly proximate the seed area. 
     
     
         22 . The method of  claim 21 , wherein the heteroepitaxial layer slopes inward distal from the seed area. 
     
     
         23 . The method of  claim 16 , wherein the entire heteroepitaxial layer is grown entirely above a top surface of the selective growth mask layer. 
     
     
         24 . The method of  claim 16 , wherein the semiconductor substrate is comprised of silicon. 
     
     
         25 . The method of  claim 16 , wherein the semiconductor substrate comprises silicon having a [001] direction normal to the substrate surface. 
     
     
         26 . The method of  claim 26 , wherein removing the portion of the selective growth mask layer to expose the seed area comprises etching the insulator to expose a (001) plane of the silicon material. 
     
     
         27 . The method of  claim 16 , wherein a second linear surface dimension ranges from about 200 nm to about 5000 nm. 
     
     
         38 . The method of  claim 16 , wherein the selective growth mask layer is comprised of silicon dioxide. 
     
     
         29 . The method of  claim 16 , further comprising forming a portion of a transistor from the heteroepitaxial layer. 
     
     
         30 . The method of  claim 16 , the seed area having a linear surface dimension that ranges from about 10 nm to about 50 nm.