Methods and apparatus for verifying completion of groups of data transactions between processors

Abstract

Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.

1 .- 20 . (canceled) 
     
     
         21 . A method of acknowledging a completion of a transaction of data via an inter-processor communication (IPC) link between a first independently operable processor apparatus and a second independently operable processor apparatus, the method comprising:
 retrieving data, the retrieving based at least on one or more first data structures written by the second independently operable processor apparatus, the one or more first data structures being arranged in a prescribed order;   transacting, based at least on the prescribed order of the one or more first data structures and via a data communication interface associated with the first independently operable processor apparatus, the retrieved data; and   writing, in said prescribed order, one or more second data structures indicative of the transacting of the retrieved data, the writing enabling the first independently operable processor apparatus to verify the transaction of the retrieved data in the prescribed order.   
     
     
         22 . The method of  claim 21 , wherein:
 the one or more first data structures comprise one or more transfer descriptors configured to be written to a transfer descriptor ring; and   the one or more second data structures comprise one or more completion descriptors configured to be written to a completion descriptor ring.   
     
     
         23 . The method of  claim 22 , wherein the retrieving of the data based at least on the one or more first data structures comprises retrieving the data from one or more locations of a backing memory apparatus, the one or more locations being represented by the one or more first data structures. 
     
     
         24 . The method of  claim 23 , wherein the transfer descriptor ring, the completion descriptor ring, and the backing memory apparatus are disposed within a shared memory apparatus, the shared memory apparatus being accessible by both the first independently operable processor apparatus and the second independently operable processor apparatus. 
     
     
         25 . The method of  claim 21 , wherein the retrieving of the data based at least on the one or more first data structures comprises retrieving data contained within the one or more first data structures. 
     
     
         26 . The method of  claim 21 , wherein the writing of the one or more second data structures comprises writing a single completion descriptor, the single completion descriptor configured to represent all of the one or more first data structures arranged in the prescribed order. 
     
     
         27 . The method of  claim 21 , wherein the verification of the transaction of the retrieved data in the prescribed order comprises at least one of: (i) a notification signal by the first independently operable processor apparatus to the second independently operable processor apparatus subsequent to the writing of the one or more second data structures, or (ii) a determination, according to a time interval, by the second independently operable processor for completion of transaction of the retrieved data by checking for a presence of at least one of the one or more second data structures within a completion descriptor ring. 
     
     
         28 . The method of  claim 21 , further comprising polling, at a prescribed interval, a transfer descriptor ring for an availability of one or more first data structures. 
     
     
         29 . The method of  claim 28 , wherein the polling is performed based at least on one or more processing considerations, the one or more processing considerations comprising at least one of: (i) power consumption associated with at least one of the first or the second independently operable processor apparatus, (ii) processing limitations associated with at least one of the first or the second independently operable processor apparatus, or (iii) application requirements associated with at least one of the first or the second independently operable processor apparatus. 
     
     
         30 . An independently operable processor apparatus comprising:
 logic configured to, when operated:
 access one or more payloads according to one or more first data structures, the one or more first data structures written to a first data structure array by a second independently operable processor apparatus, the one or more payloads being accessible at a storage apparatus associated with both the independently operable processor apparatus and the second independently operable processor apparatus; 
 cause transmission of the accessed one or more payloads (i) based on the one or more first data structures, and (ii) according to a sequence associated with the one or more first data structures; and 
 enable the second independently operable processor apparatus to verify a completion of the transaction of the one or more payloads according to the sequence, the enablement comprising placement of one or more second data structures in a second data structure array, the one or more second data structures being indicative of at least the transmission of the one or more payloads. 
   
     
     
         31 . The independently operable processor apparatus of  claim 30 , wherein:
 the independently operable processor apparatus comprises a baseband processor apparatus;   the second independently operable processor apparatus comprises an application processor apparatus configured to be in data communication with the baseband processor apparatus; and   the transmission comprises a wireless transmission via a modem associated with the baseband processor apparatus.   
     
     
         32 . The independently operable processor apparatus of  claim 30 , wherein:
 the one or more first data structures comprise one or more transfer descriptors (TDs) configured to reference a physically contiguous memory buffer of the storage apparatus;   the first data structure array comprises a transfer descriptor ring configured to hold a plurality of TDs;   the one or more second data structures comprise one or more completion descriptors (CDs) configured to indicate a completion of a transaction of data associated with a corresponding TD; and   the second data structure array comprises a completion descriptor ring configured to hold a plurality of CDs.   
     
     
         33 . The independently operable processor apparatus of  claim 30 , wherein a given one of the one or more second data structures is configured to correspond to (i) a corresponding one of the one or more first data structures, (ii) multiple ones of the one or more first data structures, or (iii) a portion of one of the one or more first data structures. 
     
     
         34 . The independently operable processor apparatus of  claim 30 , wherein the independently operable processor apparatus is further configured to periodically check the first data structure array for additional one or more first data structures written by the second independently operable processor apparatus. 
     
     
         35 . The independently operable processor apparatus of  claim 30 , wherein the independently operable processor apparatus is further configured to, upon the completion of the transaction of the one or more payloads, transmit a notification to the second independently operable processor apparatus, the notification comprising at least one of a message signaled interrupt (MSI) or a doorbell signal. 
     
     
         36 . An independently operable processor apparatus comprising:
 logic configured to, when operated:
 write one or more first data structures in a prescribed order to a first data structure array, the one or more first data structures being configured to describe data to be transacted by another independently operable processor apparatus; 
 cause the another independently operable processor apparatus to retrieve the data based at least on the one or more first data structures written in the prescribed order; 
 receive one or more second data structures configured to indicate a transaction of the data by the another independently operable processor apparatus; and 
 verify a completion of the transaction of the data in the prescribed order based at least on the received one or more second data structures. 
   
     
     
         37 . The independently operable processor apparatus of  claim 36 , wherein the independently operable processor apparatus is further configured to check for one or more additional second data structures at a second data structure array at a predetermined time interval or a dynamic time interval. 
     
     
         38 . The independently operable processor apparatus of  claim 36 , wherein the independently operable processor apparatus is further configured to remove the one or more first data structures from the first data structure array in response at least to the verification of the completion of the transaction of the data in the prescribed order. 
     
     
         39 . The independently operable processor apparatus of  claim 36 , wherein the one or more first data structures written to the first data structure array comprise one or more transfer descriptors (TDs) written to a transfer descriptor ring, and the one or more second data structures comprise one or more completion descriptors (CDs) configured to be written to a completion descriptor ring. 
     
     
         40 . The independently operable processor apparatus of  claim 39 , wherein a given TD of the one or more TDs is configured to:
 (i) indicate a location of corresponding at least portion of the data to be transacted stored on a memory apparatus, the memory apparatus being configured to be accessible by the independently operable processor apparatus and the another independently operable processor apparatus, or   (ii) encapsulate at least a portion of the data to be transacted, the encapsulation allowing the at least portion to be retrieved by the another independently operable processor apparatus from within the given TD.