US2020194359A1PendingUtilityA1

Power converter having a conductive clip

Assignee: TEXAS INSTRUMENTS INCPriority: Mar 19, 2018Filed: Feb 25, 2020Published: Jun 18, 2020
Est. expiryMar 19, 2038(~11.6 yrs left)· nominal 20-yr term from priority
H10W 90/766H10W 90/756H10W 90/753H10W 74/00H10W 72/07336H10W 72/5475H10W 72/871H10W 72/652H10W 72/60H10W 72/30H10W 70/475H10W 70/427H10W 70/20H10W 44/601H10W 70/63H10W 72/884H10W 90/754H10W 90/00H10W 90/734H10W 90/811H10W 40/778H02M 3/003H02M 1/44H02M 3/158H01L 2224/49111H01L 2224/37147H01L 24/32H01L 2224/48247H01L 23/642H01L 23/49575H01L 2224/48137H01L 23/49589H01L 2924/30107H01L 2924/14H01L 23/492H01L 2224/40245H01L 23/49551H01L 2924/1033H01L 2924/13091H01L 2224/83801H01L 24/37H01L 24/41H01L 24/40H01L 2924/181H01L 2224/73221
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Claims

Abstract

A power supply module includes a metallic clip including a plate having an area and a first and a second ridge on opposite sides of the plate. The ridges bent in the same direction away from the plate. The first and the second ridges conductively attached to the substrate, where the substrate is of insulating material integral with metal traces, the plate roofing over the substrate between the ridges. A first MOS field-effect transistor (FET) chip and, horizontally side-by-side, a second MOSFET chip are attached and wire bonded to the substrate under the plate. The drain of the first MOSFET is connected to the input terminal of the module, the source of the first MOSFET is tied to the drain of the second MOSFET, and the source of the second MOSFET, together with the second ridge, is connected to ground. A driver and controller chip is attached to the substrate under the plate and wire bonded to the gates of the first and second MOSFET. A capacitor is attached to the substrate under the clip plate and conductively connected to the first clip ridge and to the drain of the first MOSFET.

Claims

exact text as granted — not AI-modified
We claim: 
     
         1 . A method of manufacturing a semiconductor package comprising:
 assembling a passive component on a substrate of insulating material with metal traces;   assembling on the substrate, horizontally and side-by-side a chip, a chip with a first MOS field-effect transistor (FET), a chip with a second MOSFET, and a chip with a driver and controller circuit;   connecting by wire bonding and traces, a drain of a first MOSFET to an input terminal of the semiconductor package, a source of the first MOSFET to a drain of a second MOSFET, a source of the second MOSFET to a ground terminal, and gates of the first MOSFET and the second MOSFET to the driver-and-controller terminals;   connecting the passive component to the drain of the first MOSFET and the input terminal of the semiconductor package;   providing a plate having an area and a first and a second ridge on opposite sides of the plate, the first ridge and the second ridge bent in the same direction away from the plate; and   attaching the first ridge and the second ridge conductively to the substrate, the first ridge coupled to the passive component and the second ridge coupled to the ground terminal.   
     
     
         2 . The method of  claim 1 , wherein the plate and the first and second ridges together form a clip. 
     
     
         3 . The method of  claim 2  further comprising filling the space between the substrate and the clip with a packaging material, thereby covering the assembled chips and passive components while leaving the outer surfaces of the clip and the substrate free of packaging material. 
     
     
         4 . The method of  claim 1 , wherein the passive component is a capacitor. 
     
     
         5 . The method of  claim 1 , wherein the first ridge and the second ridge are at acute angles with respect to the plane along the surface of the plate. 
     
     
         6 . The method of  claim 1 , wherein the plate roofs over a portion of the substrate between the first ridge and the second ridge. 
     
     
         7 . The method of  claim 1 , wherein the driver chip and the controller chip are located horizontally side-by-side. 
     
     
         8 . The method of  claim 1 , wherein the insulating material is ceramic material. 
     
     
         9 . A method for fabricating a semiconductor package comprising:
 assembling a capacitor on a substrate with metal traces;   assembling on the substrate a chip with a first MOS field-effect transistor (FET), a chip with a second MOSFET, and a chip with a driver and controller circuit;   connecting by wire bonding and traces, a drain of the first MOSFET to an input terminal of the semiconductor package, a source of the first MOSFET to a drain of the second MOSFET, a source of the second MOSFET to a ground, and gates of MOSFET to driver-and-controller terminals;   connecting the capacitor to the drain of the first MOSFET and the input terminal of the semiconductor package;   providing a clip including a plate having an area and a first and a second ridge on opposite sides of the plate, the first and a second ridges bent in the same direction away from the plate; and   attaching the ridges conductively to the substrate so that the area of the plate forms a roof over the assembled chips and passive components, the first ridge is tied to the capacitor and the second ridge is tied to ground;   
     
     
         10 . The method of  claim 9  further comprising filling the space between the substrate and the clip with a packaging material, thereby covering the assembled chips and passive components while leaving the outer surfaces of the clip and the substrate free of packaging material. 
     
     
         11 . The method of  claim 9  wherein the first and the second MOSFETs are made of gallium nitride. 
     
     
         12 . The method of  claim 9  wherein the substrate is made of a ceramic material including at least one patterned conductive layer. 
     
     
         13 . The method of  claim 9  wherein the clip is of metal. 
     
     
         14 . The method of  claim 9  wherein the clip is selected from a group consisting of copper, copper alloy, aluminum, silver, graphene, and material of high thermal conductivity. 
     
     
         15 . The method of  claim 9 , wherein the plate roofs over a portion of the substrate between the first ridge and the second ridge. 
     
     
         16 . The semiconductor package of  claim 9 , wherein the semiconductor package functions as a power supply module.

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