Memristor based multithreading

Abstract

A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.

We claim: 
     
         1 . A device that comprises:
 a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions;   multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and   a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages;   wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.   
     
     
         2 . The device according to  claim 1 , wherein the memristor based registers comprise spin torque transfer magnetoresistive memory elements. 
     
     
         3 . The device according to  claim 1 , wherein the memristor based registers comprise resistive memory elements. 
     
     
         4 . The device according to  claim 3 , wherein the resistive memory elements are formed in close proximity to the multiple pipeline stages. 
     
     
         5 . The device according to  claim 3 , wherein the resistive memory elements are positioned directly above portions of the set of multiple pipeline stages. 
     
     
         6 . The device according to  claim 1 , wherein duration of the thread switch does not a time required to re-fill the pipeline. 
     
     
         7 . The device according to  claim 1 , wherein each pipeline stage is followed by a memristor based register. 
     
     
         8 . The device according to  claim 1 , wherein the storage of the state of the first thread of instructions at the multiple memristor based registers is preceded by extracting the state of the first thread of instructions from the set of multiple pipeline stages. 
     
     
         9 . The device according to  claim 8 , wherein an aggregate duration of the extracting of the state of the first thread of instructions and the storage of the state of the first thread of instructions exceeds a duration of the provision of the state of the other thread of instructions. 
     
     
         10 . The device according to  claim 1 , wherein the multiple memristor based registers are arranged to store a state of each one out of multiple other thread of instructions that differ from the first thread of instructions; and wherein the control circuit is arranged to control thread switches between any instructions out of the first thread if instructions and any one of the other threads of instructions. 
     
     
         11 . The device according to  claim 10 , wherein the multiple other thread of instructions exceed three threads of instructions. 
     
     
         12 . The device according to  claim 10 , wherein the multiple other thread of instructions exceed ten threads of instructions. 
     
     
         13 . The device according to  claim 10 , wherein the multiple memristor based registers comprises multiple layers, wherein each layer is dedicated for storing the status of a single other thread of instructions. 
     
     
         14 . The device according to  claim 10  wherein the memristor based registers comprise resistive memory elements; wherein each other thread of instructions is stored in a memristive-based layer of the memristor based registers. 
     
     
         15 . A method, comprising:
 executing, by a set of multiple pipeline stages, a first thread of instructions;   storing, by multiple memristor based registers, a state of another thread of instructions that differs from the first thread of instructions; and   executing a thread switch between the first thread of instructions and the other thread of instructions; wherein the executing of the thread switch comprises:
 storing a state of the first thread of instructions at the multiple memristor based registers; and 
 providing the state of the other thread of instructions by the set of multiple pipeline stages; wherein the state of the other thread of instructions facilitates an executing of the other thread of instructions. 
   
     
     
         16 . The method according to  claim 15 , wherein the memristor based registers comprise spin torque transfer magnetoresistive memory elements. 
     
     
         17 . The method according to  claim 15 , wherein the memristor based registers comprise resistive memory elements. 
     
     
         18 . The method according to  claim 17 , wherein the resistive memory elements are formed in close proximity to the multiple pipeline stages. 
     
     
         19 . The method according to  claim 17 , wherein the resistive memory elements are positioned directly above portions of the set of multiple pipeline stages. 
     
     
         20 . The method according to  claim 15 , wherein a duration of the thread switch does not exceed 3 clock cycles of a clock signal provided to the set of multiple pipeline stages. 
     
     
         21 . The method according to  claim 15 , wherein each pipeline stage is followed by a memristor based register. 
     
     
         22 . The method according to  claim 15 , wherein the storing of the state of the first thread of instructions at the multiple memristor based registers is preceded by extracting the state of the first thread of instructions from the set of multiple pipeline stages. 
     
     
         23 . The method according to  claim 8 , wherein an aggregate duration of the extracting of the state of the first thread of instructions and the storing of the state of the first thread of instructions exceeds a duration of the provision of the state of the other thread of instructions. 
     
     
         24 . The method according to  claim 15 , comprising storing by the multiple memristor based registers a state of each one out of multiple other thread of instructions that differ from the first thread of instructions; and wherein the method comprises executing a thread switch between any thread of instructions out of the first thread of instructions and the multiple other threads of instructions. 
     
     
         25 . The method according to  claim 24 , wherein the multiple other thread of instructions exceed three threads of instructions. 
     
     
         26 . The method according to  claim 24 , wherein the multiple other thread of instructions exceed ten threads of instructions. 
     
     
         27 . The method according to  claim 24 , wherein the multiple memristor based registers comprises multiple layers, wherein the storing comprise storing by each layer a status of a single other thread of instructions. 
     
     
         28 . The method according to  claim 24  wherein the memristor based registers comprise resistive memory elements; wherein the method comprises storing each other thread of instructions is in a memristive-based layer of the memristor based registers.