High-Speed Switch with Accelerated Switching Time

Abstract

A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.

What is claimed is: 
     
         1 . A multiport switch comprising:
 (a) at least one switch branch comprising:
 (1) switch control input; 
 (2) a field effect transistor (FET) having a gate, source and drain; 
 (3) a reset circuit having an signal input, signal output, reset control input and reference input signal output being coupled to the gate of the FET, the reset circuit configured to reset the FET by connecting the gate of the FET to the signal input when the reset circuit is inactive and to the reference input when the reset circuit is active; 
   (b) a reset processor having a reset processor input coupled to the switch control input and a reset processor output coupled to the reset control input, the reset processor configured to output a reset pulse from the reset processor output in response to a change in the state of a signal received at the reset processor input.