Semiconductor device and a method of manufacturing the same

Abstract

A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.

What is claimed is: 
     
         1 . A semiconductor device including a p-channel conductivity type field effect transistor formed on a semiconductor substrate,
 wherein a compressive stress applying film is formed over a first gate electrode and source and drain regions and a sidewall spacer is formed on the semiconductor substrate and a side surface of the first gate electrode, for applying a compressive stress to a first channel formation region of the p-channel conductivity type field effect transistor,   wherein the compressive stress is applied by both the compressive stress applying film and the sidewall spacer in a gate length direction of the first gate electrode,   wherein, due to the application of the compressive stress by both the compressive stress applying film and the sidewall spacer, a lattice constant of a material comprising the semiconductor substrate in the first channel formation region is smaller than a lattice constant of the material under a state when the compressive stress is not applied to the first channel formation region, and   wherein the compressive stress applying film and the sidewall spacer is configured to increase a current which flows in the first channel formation region in response to the compressive stress.   
     
     
         2 . A semiconductor device according to the  claim 1 ,
 wherein the sidewall spacer includes a silicon nitride film.   
     
     
         3 . A semiconductor device according to the  claim 1 ,
 wherein the compressive stress is equal or greater than −900 MPa.   
     
     
         4 . A semiconductor device according to the  claim 1 ,
 wherein the compressive stress applying film is configured to apply the compressive stress in an amount sufficient to increase the current which flows into the first channel formation region by not less than 15%.   
     
     
         5 . A semiconductor device according to the  claim 1 , further including an n-channel conductivity type field effect transistor formed on the semiconductor substrate,
 wherein a tensile stress applying film is formed over a second gate electrode and source and drain regions of the n-channel conductivity type field effect transistor for applying a tensile stress to a second channel formation region of the n-channel conductivity type field effect transistor, and   wherein the tensile stress is applied by the tensile stress applying film in a gate length direction of the second gate electrode of the n-channel conductivity type field effect transistor.   
     
     
         6 . A semiconductor device according to the  claim 5  wherein, due to the application of the tensile stress by the tensile stress applying film, a lattice constant of the material comprising the semiconductor substrate in the second channel formation region is greater than a lattice constant of the material under a state when the tensile stress is not applied to the second channel formation region, and
 wherein the tensile stress applying film is configured to increase a current which flows in the second channel formation region in response to the tensile stress. 
 
     
     
         7 . A semiconductor device according to the  claim 6 ,
 wherein the p-channel conductivity type field effect transistor includes a source and drain regions and P-type semiconductor extension regions which extend under the first gate electrode.   
     
     
         8 . A semiconductor device according to  claim 1 , wherein the compressive stress applying film is comprised of silicon nitride. 
     
     
         9 . A semiconductor device according to  claim 1 , further comprising a silicide layer formed between an upper surface of the first gate electrode and a lower surface of the compressive stress applying film. 
     
     
         10 . A semiconductor device according to  claim 5 , the compressive stress applying film and the tensile stress applying film are comprised of silicon nitride. 
     
     
         11 . A semiconductor device according to  claim 5 , further comprising a first silicide layer formed between an upper surface of the first gate electrode and a lower surface of the compressive stress applying film and a second silicide layer formed between an upper surface of the second gate electrode and a lower surface of the tensile stress applying film. 
     
     
         12 . A semiconductor device according to the  claim 1 , wherein the compressive stress applying film is processed during formation thereof to provide the compressive stress to the first channel formation region of the P-channel conductivity type field effect transistor, in an amount which is equal or greater than −900 MPa, by subjecting the compressive stress applying film during formation thereof to a high frequency power of 600-700 W.