Packed data operation mask shift processors, methods, systems, and instructions

Abstract

A method of an aspect includes receiving a packed data operation mask shift instruction. The packed data operation mask shift instruction indicates a source having a packed data operation mask, indicates a shift count number of bits, and indicates a destination. The method further includes storing a result in the destination in response to the packed data operation mask shift instruction. The result includes a sequence of bits of the packed data operation mask that have been shifted by the shift count number of bits. Other methods, apparatus, systems, and instructions are disclosed.

What is claimed is: 
     
         1 . A processor comprising:
 a decode unit to decode instructions, including a first plurality of instructions that are to indicate general-purpose registers, and a second plurality of instructions that are to indicate packed data operation mask registers, the second plurality of instructions including a first instruction, the first instruction to indicate a packed data operation mask register, of the packed data operation mask registers, which is to store a packed data operation mask, the first instruction to indicate a shift count number of bits, and the first instruction to indicate a destination, wherein the packed data operation mask register can be used by other instructions for predication and supports both merging masking and zeroing masking; and   an execution unit coupled with the decode unit, the execution unit to perform the first instruction to:
 generate a result; and 
 store the result in the destination, the result to include a sequence of bits of the packed data operation mask shifted by the shift count number of bits with a same number of zeroes shifted in as the shift count number of bits, and a plurality of most significant bits of the result to be zero. 
   
     
     
         2 . The processor of  claim 1 , wherein the execution unit to generate the result is to right shift the sequence of bits of the packed data operation mask by the shift count number of bits with the same number of zeroes shifted in at left as the shift count number of bits. 
     
     
         3 . The processor of  claim 1 , wherein the execution unit to generate the result is to left shift the sequence of bits of the packed data operation mask by the shift count number of bits with the same number of zeroes shifted in at right as the shift count number of bits. 
     
     
         4 . The processor of  claim 1 , wherein the packed data operation mask is an N-bit packed data operation mask, wherein the shift count number of bits is an M-bit shift count number of bits, and wherein the execution unit to perform the first instruction is to store the result that is to include:
 (a) in a least significant N-bits of the destination, an (N−M)-bit sequence of the bits of the N-bit packed data operation mask that is to have been shifted by the M-bit shift count number of bits, and M-bits that all are to have a same bit value; and   (b) in a most significant remainder of the destination a plurality of bits that all are to have a value of zero.   
     
     
         5 . The processor of  claim 1 , wherein the first instruction is to specify the shift count number of bits in an immediate, wherein an opcode of the first instruction implicitly indicates a size of data to be shifted. 
     
     
         6 . The processor of  claim 1 , wherein all but one of the packed data operation mask registers can be used for the predication and support both the merging masking and the zeroing masking. 
     
     
         7 . The processor of  claim 1 , the execution unit including shift circuitry to shift the sequence of bits by the shift count number of bits. 
     
     
         8 . A processor comprising:
 a decode unit to decode instructions, including a first plurality of instructions that are to specify general-purpose registers and a second plurality of instructions that are to specify packed data operation mask registers, the second plurality of instructions including a first instruction having bits to explicitly specify a source packed data operation mask register of the packed data operation mask registers which is to store a source packed data operation mask, the first instruction having bits to explicitly specify a destination packed data operation mask register of the packed data operation mask registers, and the first instruction having an 8-bit immediate to provide a shift count number of bits, wherein the source packed data operation mask register can be used for predication and supports both merging masking and zeroing masking; and   an execution unit coupled with the decode unit, the execution unit to perform the first instruction to:
 generate a result; and 
 store the result in the destination packed data operation mask register, bits [31:0] of the result to include a value of bits [31:0] of the source packed data operation mask right shifted by the shift count number of bits with a same number of zeroes at left as the shift count number of bits, and all bits of the result that are more significant than bit-31 of the result to be zero. 
   
     
     
         9 . The processor of  claim 8 , wherein an opcode of the first instruction implicitly indicates that 32-bits of the source packed data operation mask are to be right shifted. 
     
     
         10 . The processor of  claim 9 , wherein the decode unit is also to decode a second instruction that has an opcode that implicitly indicates that 8-bits of a source packed data operation mask are to be right shifted. 
     
     
         11 . The processor of  claim 9 , wherein the decode unit is also to decode a third instruction that has an opcode that implicitly indicates that 32-bits of a source packed data operation mask are to be left shifted. 
     
     
         12 . The processor of  claim 8 , wherein all but one of the packed data operation mask registers can be used for the predication and support both the merging masking and the zeroing masking. 
     
     
         13 . The processor of  claim 8 , the execution unit including shift circuitry to right shift the bits [31:0] of the source packed data operation mask by the shift count number of bits, and wherein the result consists of 64-bits. 
     
     
         14 . The processor of  claim 8 , wherein the first instruction is to have an instruction format that includes a three-byte VEX Prefix. 
     
     
         15 . A processor comprising:
 a decode unit to decode instructions, including a first plurality of instructions that are to specify general-purpose registers and a second plurality of instructions that are to specify packed data operation mask registers, the second plurality of instructions including a first instruction having bits to explicitly specify a source packed data operation mask register of the packed data operation mask registers which is to store a source packed data operation mask, the first instruction having bits to explicitly specify a destination packed data operation mask register of the packed data operation mask registers, and the first instruction having an 8-bit immediate to provide a shift count number of bits, wherein the source packed data operation mask register can be used for predication and supports both merging masking and zeroing masking; and   an execution unit coupled with the decode unit, the execution unit to perform the first instruction to:
 generate a result; and 
 store the result in the destination packed data operation mask register, bits [7:0] of the result to include a value of bits [7:0] of the source packed data operation mask right shifted by the shift count number of bits with a same number of zeroes at left as the shift count number of bits, and all bits of the result that are more significant than bit- 7  of the result to be zero. 
   
     
     
         16 . The processor of  claim 15 , the execution unit including shift circuitry to right shift the bits [7:0] of the source packed data operation mask by the shift count number of bits, and wherein all but one of the packed data operation mask registers can be used for the predication and support both the merging masking and the zeroing masking. 
     
     
         17 . The processor of  claim 15 , wherein an opcode of the first instruction implicitly indicates that 8-bits of the source packed data operation mask are to be right shifted, wherein the decode unit is also to decode a second instruction that has an opcode that implicitly indicates that 8-bits of a source packed data operation mask are to be left shifted, and wherein the first instruction is to have an instruction format that includes a three-byte VEX Prefix. 
     
     
         18 . An apparatus comprising:
 an instruction converter selected from a group of a binary translator and an instruction emulator to convert a shift right instruction of a first complex instruction set computing (CISC) instruction set to one or more corresponding instructions of a second different instruction set, the shift right instruction having bits to explicitly specify a source packed data operation mask register, of a set of packed data operation mask registers, that is to store a source packed data operation mask, and having an 8-bit immediate to provide a shift count number of bits, wherein the source packed data operation mask register can be used by other instructions of the first CISC instruction set for predication and supports both merging masking and zeroing masking; and   a processor coupled with the instruction converter, the processor to decode and execute the one or more corresponding instructions of the second instruction set, the processor, due to performing the one or more corresponding instructions of the second instruction set to store a result in a destination, bits [31:0] of the result to include a value of bits [31:0] of the source packed data operation mask right shifted by the shift count number of bits with a same number of zeroes at left as the shift count number of bits, and all bits of the result that are more significant than bit-32 of the result to be zero.   
     
     
         19 . The apparatus of  claim 18 , wherein the processor includes shift circuitry to right shift the bits [31:0] of the source packed data operation mask, wherein bits [63:32] of the result are all to be zeroes, wherein an opcode of the shift right instruction implicitly indicates that 32-bits of the source packed data operation mask are to be right shifted. 
     
     
         20 . The apparatus of  claim 18 , wherein the shift right instruction is to have an instruction format that includes a three-byte VEX Prefix. 
     
     
         21 . The apparatus of  claim 18 , wherein all but one of the set of the packed data operation mask registers can be used for the predication and support both the merging masking and the zeroing masking.