Double-gate mos transistor with increased breakdown voltage

Abstract

A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.

1 . A process for producing a MOS transistor, comprising:
 forming an insulated conductive gate region above a semiconductor substrate by:
 defining a first insulated conductive gate region; and 
 defining a second insulated conductive gate region over the first insulated conductive gate region; 
 wherein the first insulated conductive gate region has dimensions which protrude at least on one side beyond the second insulated conductive gate region; and 
   carrying out a tilted implantation of dopants in the semiconductor substrate through the insulated conductive gate region so as to form a source region and a drain region of the MOS transistor, wherein said source and drain regions extend underneath the insulated conductive gate region.   
     
     
         2 . The process for producing a MOS transistor according to  claim 1 , wherein forming comprises:
 forming on the semiconductor substrate a first dielectric layer;   forming on the first dielectric layer a first layer of conductive gate material;   at least partially etching the first layer of conductive gate material so as to form the first insulated conductive gate region;   forming a second dielectric layer on at least the first insulated conductive gate region;   forming on the second dielectric layer a second layer of conductive gate material; and   etching the second layer of conductive gate material so as to form the second insulated conductive gate region.   
     
     
         3 . The process for producing a MOS transistor according to  claim 2 , wherein forming and at least partially etching the first layer of conductive gate material comprises defining the first insulated conductive gate region to have a non-uniform height which includes a central zone having a first height and at least one stair zone extending from the central zone with a second height less than the first height. 
     
     
         4 . The process for producing a MOS transistor according to  claim 1 , further comprising electrically connecting the first and second insulated conductive gate regions. 
     
     
         5 . The process for producing a MOS transistor according to  claim 1 , wherein the first insulated conductive gate region protrudes from the second insulated conductive gate region at least on one side by a protrusion length, and wherein a distance between an end of a doping profile of the source region or drain region which is located under the first insulated conductive gate region and the end of the protruding portion of the first insulated conductive gate region is larger than said protrusion length.