Nonvolatile memory device and method for fabricating the same

Abstract

A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

1 . A nonvolatile memory device comprising:
 a substrate including a cell region and a peripheral circuit region;   a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially;   a semiconductor pattern connected to the substrate through the stacked structure;   a peripheral circuit element on the peripheral circuit region;   a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element; and   a lower contact connected to the peripheral circuit element through the first interlayer insulating film,   a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.   
     
     
         2 . The nonvolatile memory device of  claim 1 , further comprising:
 a second interlayer insulating film covering the stacked structure and the first interlayer insulating film; and   an upper contact connected to the lower contact through the second interlayer insulating film.   
     
     
         3 . The nonvolatile memory device of  claim 2 , wherein a width of the lower contact is larger than a width of the upper contact at the same level as a top surface of the first interlayer insulating film. 
     
     
         4 . The nonvolatile memory device of  claim 2 , wherein the lower contact and the upper contact include different materials from each other. 
     
     
         5 . The nonvolatile memory device of  claim 2 , wherein a bottom surface of the upper contact is lower than an uppermost surface of the lower contact. 
     
     
         6 . The nonvolatile memory device of  claim 1 , wherein the first interlayer insulating film covers the lowermost gate pattern of the plurality of gate patterns. 
     
     
         7 . The nonvolatile memory device of  claim 1 , wherein the lowermost gate pattern of the plurality of gate patterns extends along a top surface of the first interlayer insulating film. 
     
     
         8 . The nonvolatile memory device of  claim 1 , wherein the height of the top surface of the lower contact is substantially equal to a height of a top surface of the first interlayer insulating film. 
     
     
         9 . (canceled) 
     
     
         10 . The nonvolatile memory device of  claim 1 , wherein
 the lower contact includes a first portion directly connected to the peripheral circuit element and a second portion on the first portion, and   a width of a lowermost portion of the second portion is larger than a width of an uppermost portion of the first portion at a boundary between the first portion and the second portion.   
     
     
         11 . The nonvolatile memory device of  claim 1 , wherein
 the lower contact includes a first portion directly connected to the peripheral circuit element and a second portion on the first portion, and   with respect to a top surface of the substrate, a slope of a sidewall of the second portion is smaller than a slope of a sidewall of the first portion.   
     
     
         12 . (canceled) 
     
     
         13 . A nonvolatile memory device comprising:
 a substrate including a cell region and a peripheral circuit region;   a ground selection line on the cell region, the ground selection line extending along a top surface of the substrate;   a peripheral circuit element on the peripheral circuit region;   a first interlayer insulating film on the substrate, the first interlayer insulating film covering the ground selection line and the peripheral circuit element;   a mold structure on the first interlayer insulating film of the cell region, the mold structure including a word line and an insulation pattern stacked alternately;   a second interlayer insulating film on the first interlayer insulating film, the second interlayer insulating film covering the mold structure and the peripheral circuit region;   a semiconductor pattern connected to the substrate through the ground selection line, the first interlayer insulating film, and the mold structure; and   a peripheral circuit contact including a lower contact and an upper contact, the lower contact being connected to the peripheral circuit element through the first interlayer insulating film, and the upper contact being connected to the lower contact through the second interlayer insulating film.   
     
     
         14 . The nonvolatile memory device of  claim 13 , further comprising a plurality of cell contacts connected to the word line through the second interlayer insulating film. 
     
     
         15 . The nonvolatile memory device of  claim 14 , wherein the upper contact and the plurality of cell contacts have substantially the same material composition. 
     
     
         16 . (canceled) 
     
     
         17 . The nonvolatile memory device of  claim 13 , further comprising a sacrificial pattern extending along a profile of a top surface of the peripheral circuit element in the first interlayer insulating film,
 wherein the lower contact is connected to the peripheral circuit element through the sacrificial pattern.   
     
     
         18 . The nonvolatile memory device of  claim 17 , wherein a thickness of the sacrificial pattern is substantially equal to a thickness of the ground selection line. 
     
     
         19 . (canceled) 
     
     
         20 . The nonvolatile memory device of  claim 13 , further comprising, between the ground selection line and the word line, a dummy word line extending along a top surface of the first interlayer insulating film of the cell region. 
     
     
         21 . The nonvolatile memory device of  claim 20 , further comprising a sacrificial pattern extending along the top surface of the first interlayer insulating film of the peripheral circuit region,
 wherein a thickness of the sacrificial pattern is substantially equal to a thickness of the dummy word line.   
     
     
         22 . (canceled) 
     
     
         23 . The nonvolatile memory device of  claim 13 , wherein
 the peripheral circuit element includes a peripheral circuit gate pattern and an impurity region in the substrate on both sides of the peripheral circuit gate pattern,   the lower contact includes a first lower contact and a second lower contact, the first lower contact being connected to the impurity region, and the second lower contact being separated from the first lower contact and being connected to the peripheral circuit gate pattern,   the upper contact includes a first upper contact and a second upper contact, the first upper contact being connected to the first lower contact, and the second upper contact being separated from the first upper contact and being connected to the second lower contact, and   a height of a bottom surface of the first upper contact and a height of a bottom surface of the second upper contact are different from each other.   
     
     
         24 . A nonvolatile memory device comprising:
 a substrate including a cell region and a peripheral circuit region;   a stacked structure on the cell region, the stacked structure including a first gate pattern, a second gate pattern, and a third gate pattern separated from each other and stacked sequentially from a top surface of the substrate;   a semiconductor pattern connected to the substrate through the stacked structure;   a peripheral circuit element on the peripheral circuit region;   a first interlayer insulating film on the substrate, the first interlayer insulating film covering the first gate pattern and the peripheral circuit element; and   a lower contact connected to the peripheral circuit element through the first interlayer insulating film,   a separation distance between the first gate pattern and the second gate pattern being greater than a separation distance between the second gate pattern and the third gate pattern, and   a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of the third gate pattern.   
     
     
         25 . The nonvolatile memory device of  claim 24 , wherein the second gate pattern is a dummy word line extending along a top surface of the first interlayer insulating film of the cell region. 
     
     
         26 .- 35 . (canceled)