US2020176461A1PendingUtilityA1

Silicon wafer

Assignee: SUMCO CORPPriority: Jul 10, 2017Filed: Jun 6, 2018Published: Jun 4, 2020
Est. expiryJul 10, 2037(~11 yrs left)· nominal 20-yr term from priority
H10P 14/69433H10P 14/69215H10P 14/6682H10P 14/6336H10P 14/662H01L 27/11551H01L 27/11524H10P 72/0616H10P 90/12C30B 29/06H10B 41/20C23C 16/402H10P 14/2905H10P 90/128H10P 90/14H10B 41/35
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Claims

Abstract

A silicon wafer is capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer according to the present invention is a silicon wafer in which there is formed a multilayered film constituting a semiconductor device layer on one main surface thereof in a device process, which is warped in a bowl shape due to an isotropic film stress of the multilayered film, and which has a (111) plane orientation.

Claims

exact text as granted — not AI-modified
1 . A silicon wafer in which there is formed a multilayered film constituting a semiconductor device layer on one main surface thereof in a device process, which is warped in a bowl shape due to an isotropic film stress of the multilayered film, and which has a (111) plane orientation. 
     
     
         2 . The silicon wafer as claimed in  claim 1 , wherein the oxygen concentration of the silicon wafer is 8.0×10 17  atoms/cm 3  or more (ASTM F-121, 1979). 
     
     
         3 . The silicon wafer as claimed in  claim 1 , wherein the semiconductor device layer includes a 3DNAND flash memory. 
     
     
         4 . A silicon wafer in which there is formed a multilayered film constituting a semiconductor device layer on one main surface thereof in a device process, which is warped in a saddle shape due to an anisotropic film stress of the multilayered film, and which has a (110) plane orientation and a <111> notch orientation. 
     
     
         5 . The silicon wafer as claimed in  claim 4 , wherein the oxygen concentration of the silicon wafer is 6.0×10 17  atoms/cm 3  or more (ASTM F-121, 1979). 
     
     
         6 . The silicon wafer as claimed in  claim 4 , wherein the semiconductor device layer includes a 3DNAND flash memory.

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