Semiconductor structure with capacitor landing pad and method of make the same

Abstract

The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor structure with capacitor landing pad includes a substrate having a plurality of contact structures, a first dielectric layer disposed on the substrate and the contact structures, and a plurality of capacitor landing pads, each of the capacitor landing pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the capacitor landing pads presents a shape of a wide top and a narrow bottom and a top surface of the capacitor landing pads have a concave shape.

What is claimed is: 
     
         1 . A semiconductor structure with conductive pad comprising:
 a substrate having a plurality of contact structures therein;   a first dielectric layer disposed on the substrate and the contact structures; and   a plurality of conductive pads, each of the conductive pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the conductive pads presents a shape of a wide top and a narrow bottom and a top surface of the conductive pads have a concave shape.   
     
     
         2 . The semiconductor structure with conductive pad according to  claim 1 , further comprising a barrier layer interposed between the conductive pad and the first dielectric layer and the contact structure. 
     
     
         3 . The semiconductor structure with conductive pad according to  claim 1 , further comprising a second dielectric layer disposed on the first dielectric layer and the conductive pads, wherein a recess is formed in the second dielectric layer to expose the conductive pads, and an exposed top surface of the conductive pads are recessed greater in amplitude than a unexposed top surface of the conductive pads. 
     
     
         4 . The semiconductor structure with conductive pad according to  claim 3 , wherein the second dielectric layer comprises a silicon carbonitride layer and a silicon oxide layer.