Package module

Abstract

A package module includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and having a connection pad electrically connected to the one or more redistribution layers, a plurality of electronic components disposed on the connection structure and electrically connected to the one or more redistribution layers, one or more frames disposed on the connection structure, and an encapsulant disposed on the connection structure, and respectively covering at least portions of the semiconductor chip, the plurality of electronic components, and the one or more frames. At least a portion of an outer side surface of the encapsulant is coplanar on the same level as at least a portion of an outer side surface of at least one of the one or more frames.

What is claimed is: 
     
         1 . A package module comprising:
 a connection structure including one or more redistribution layers;   a semiconductor chip disposed on the connection structure and having a connection pad electrically connected to the one or more redistribution layers;   a plurality of electronic components disposed on the connection structure and electrically connected to the one or more redistribution layers;   one or more frames disposed on the connection structure; and   an encapsulant disposed on the connection structure, and respectively covering at least portions of the semiconductor chip, the plurality of electronic components, and the one or more frames,   wherein at least a portion of an outer side surface of the encapsulant is coplanar on the same level as a level of at least a portion of an outer side surface of at least one of the one or more frames.   
     
     
         2 . The package module of  claim 1 , wherein at least one of the one or more frames is disposed between the plurality of electronic components. 
     
     
         3 . The package module of  claim 1 , wherein the encapsulant comprises a first encapsulant covering at least a portion of each of the plurality of electronic components and the one or more frames, and a second encapsulant covering at least a portion of each of the semiconductor chip and the first encapsulant,
 wherein at least a portion of the outer side surface of the first encapsulant is coplanar on the same level as a level of at least a portion of the outer side surface of at least one of the one or more frames.   
     
     
         4 . The package module of  claim 3 , further comprising a penetration portion penetrating through the first encapsulant,
 wherein the semiconductor chip is disposed in the penetration portion, and   the second encapsulant fills at least a portion of the through portion.   
     
     
         5 . The package module of  claim 4 , further comprising:
 a first metal layer disposed on an outer side surface of each of the one or more frames, and extending to at least one surface of each of the one or more frames; and   a second metal layer disposed on a wall surface of the penetration portion and extending to at least one surface of the first encapsulant.   
     
     
         6 . The package module of  claim 5 , further comprising:
 a backside metal layer disposed on the second encapsulant;   a first metal via penetrating through the first and second encapsulants, and connecting the backside metal layer to the first metal layer; and   a second metal via penetrating through the second encapsulant and connecting the backside metal layer to the second metal layer.   
     
     
         7 . The package module of  claim 4 , wherein at least one of the one or more frames comprises a plurality of conductor pattern layers electrically connected to each other,
 wherein the plurality of conductor pattern layers are electrically connected to the one or more redistribution layers.   
     
     
         8 . The package module of  claim 7 , further comprising:
 a backside conductor pattern layer disposed on the second encapsulant; and   a backside conductor via penetrating through the first and second encapsulants and electrically connecting the backside conductor pattern layer to the plurality of conductor pattern layers.   
     
     
         9 . The package module of  claim 7 , wherein at least one of the one or more frames comprises a first insulating layer, a first conductor pattern layer embedded in the first insulating layer in such a manner that one surface of the first conductor pattern layer is exposed to the first insulating layer, a second conductor pattern layer disposed on a side of the first insulating layer, opposing a side of the first insulating layer, in which the first conductor pattern layer is embedded, a second insulating layer disposed on the side of the first insulating layer, opposing the side of the first insulating layer, in which the first conductor pattern layer is embedded, the second insulating layer covering the second conductor pattern layer, and a third conductor pattern layer disposed on a side of the second insulating layer, opposing a side of the second insulating layer, in which the second conductor pattern layer is embedded,
 wherein the plurality of conductor pattern layers comprise the first to third conductor pattern layers.   
     
     
         10 . The package module of  claim 7 , wherein at least one of the one or more frames comprises a first insulating layer, and first and second conductor pattern layers disposed on both surfaces of the first insulating layer, respectively, and
 the plurality of conductor pattern layers comprise the first and second conductor pattern layers.   
     
     
         11 . The package module of  claim 10 , wherein at least one of the one or more frames further comprises second and third insulating layers disposed on both surfaces of the first insulating layer to cover the first and second conductor pattern layers, respectively, a third conductor pattern layer disposed on an opposite side of a side of the second insulating layer in which the first conductor pattern layer is embedded, and a fourth conductor pattern layer disposed on an opposite side of a side of the third insulating layer in which the second conductor pattern layer is embedded, and
 the plurality of conductor pattern layers comprise the first to fourth conductor pattern layers.   
     
     
         12 . The package module of  claim 1 , further comprising:
 a wiring member disposed on a side of each of the plurality of electronic components and the one or more frames, facing the connection structure, the wiring member including one or more wiring layers respectively electrically connected to the plurality of electronic components,   wherein the semiconductor chip has an active surface on which the connection pad is disposed and an inactive surface opposing the active surface, the active surface being in contact with the connection structure,   wherein the active surface of the semiconductor chip is located to be lower than a level of a surface of each of the plurality of electronic components in contact with the wiring member, with reference to the inactive surface of the semiconductor chip.   
     
     
         13 . The package module of  claim 12 , wherein the plurality of electronic components comprise at least one of a capacitor and an inductor. 
     
     
         14 . The package module of  claim 1 , further comprising a metal film covering an upper surface and an outer side surface of the encapsulant, an outer side surface of each of the one or more frames, and an outer side surface of the connection structure. 
     
     
         15 . A package module comprising:
 a core structure including a plurality of electronic components, a plurality of frames, and a first encapsulant covering at least a portion of each of the plurality of electronic components and each of the plurality of frames, the core structure including a penetration portion passing through the first encapsulant;   a semiconductor chip disposed in the penetration portion and including a connection pad;   a second encapsulant covering at least a portion of each of the core structure and the semiconductor chip, the second encapsulant filling at least a portion of the penetration portion; and   a connection structure disposed on the core structure and on a surface of the semiconductor chip on which the connection pad is disposed, the connection structure including one or more redistribution layers electrically connected to the plurality of electronic components and the connection pad.   
     
     
         16 . The package module of  claim 15 , wherein at least a portion of an outer side surface of the first encapsulant is coplanar on the same level as at least a portion of an outer side surface of at least one of the plurality of frames. 
     
     
         17 . A package module comprising:
 a connection structure;   a core structure disposed on the connection structure, and including a first encapsulant, a plurality of frames and a plurality of electronic components dispersed in the first encapsulant;   a semiconductor chip disposed on the connection structure and including a redistribution layer; and   a second encapsulant covering at least a portion of each of the core structure and the semiconductor chip and separating the semiconductor chip and the core structure from each other,   wherein an outer side surface of one of the plurality of frames, an outer side surface of the first encapsulant, and an outer side surface of the second encapsulant are substantially coplanar with each other.   
     
     
         18 . The package module of  claim 17 , wherein the one of the plurality of frames includes a lower surface facing the connection structure and an upper surface opposing the lower surface thereof, and the core structure further includes a first metal layer covering inner side surfaces of the one of the plurality of frames. 
     
     
         19 . The package module of  claim 17 , wherein the core structure includes a lower surface facing the connection structure and an upper surface opposing the lower surface thereof, and
 the core structure further includes a second metal layer covering inner surfaces of the core structure facing side surfaces of the semiconductor chip.   
     
     
         20 . The package module of  claim 17 , wherein the core structure includes a lower surface facing the connection structure and an upper surface opposing the lower surface thereof,
 the core structure further includes a first metal layer covering inner side surfaces of the one of the plurality of frames and a second metal layer covering inner surfaces of the core structure facing side surfaces of the semiconductor chip, and   the package module further includes a metal film covering an upper surface of the second encapsulant and electrically connected to the first and second metal layers.