Memory devices and methods of processing security data thereof

Abstract

A memory device includes: a memory cell array including a security region configured to store security data; and a security management circuit configured to store a guard key and, responsive to receiving a data operation command for the security region, limit a data operation for the security region by comparing the guard key with an input password that is received by the memory device.

What is claimed is: 
     
         1 . A memory device comprising:
 a memory cell array comprising a security region that is configured to store security data; and   a security management circuit configured to store a guard key and, responsive to receiving a data operation command for the security region, limit a data operation for the security region by comparing the guard key with an input password that is received by the memory device.   
     
     
         2 . The memory device according to  claim 1 , wherein, in a guard key injection phase and/or a guard key update phase, the security management circuit is configured to receive the guard key from outside the memory device and to store the guard key. 
     
     
         3 . The memory device according to  claim 1 , wherein, in a memory region allocation phase, the security management circuit is configured to generate region information about the security region based on a physical address and store the generated region information, the physical address being received after a write command is input to the memory device or at the same time when the write command is input to the memory device. 
     
     
         4 . The memory device according to  claim 3 , wherein the region information comprises a start address corresponding to the security region and a size of the security region. 
     
     
         5 . The memory device according to  claim 3 , wherein the region information comprises a start address and an end address, which correspond to the security region. 
     
     
         6 . The memory device according to  claim 1 , wherein, in a memory region allocation phase, the security management circuit is configured to allocate the security region, obtain a physical address corresponding to the security region, store region information about the security region based on the obtained physical address, and provide information about the obtained physical address external to the memory device. 
     
     
         7 . The memory device according to  claim 1 , wherein, responsive to the input password being consistent with the guard key, the security management circuit is configured to control the memory device such that the memory device performs the data operation. 
     
     
         8 . The memory device according to  claim 1 , wherein, responsive to the input password being inconsistent with the guard key, the security management circuit is configured to control the memory device such that the memory device does not perform the data operation. 
     
     
         9 . The memory device according to  claim 8 , wherein, responsive to the input password being inconsistent with the guard key, the security management circuit is configured to control a column decoder and/or a row decoder of the memory device such that data is not written to the memory cell array and/or is not read from the memory cell array. 
     
     
         10 . The memory device according to  claim 1 , wherein, responsive to the input password being inconsistent with the guard key, the security management circuit is configured to output an alert signal to the outside of the memory device. 
     
     
         11 . The memory device according to  claim 1 , wherein, responsive to receiving the data operation command for the security region and not receiving the input password, the security management circuit is configured to withhold the data operation for the security region and to output a password request signal external to the memory device. 
     
     
         12 . The memory device according to  claim 1 , wherein the security management circuit comprises:
 a first memory configured to store region information about the security region;   a second memory configured to store the guard key;   an address comparison circuit configured to receive the region information from the first memory and generate a region comparison result by comparing the region information with an address input from external to the memory device;   a password comparison circuit configured to receive the guard key from the second memory and generate a password comparison result by determining if the input password is consistent with the guard key; and   a security control circuit configured to limit the data operation for the security region and/or output an alert signal external to the memory device, based on the region comparison result received from the address comparison circuit and the password comparison result received from the password comparison circuit.   
     
     
         13 . The memory device according to  claim 1 , wherein the memory device has a structure in which at least one core die is stacked on a buffer die, and
 the security management circuit is implemented in the buffer die.   
     
     
         14 . A method of processing security data of a memory device, the method comprising:
 receiving an input password;   comparing the received input password with a guard key stored in the memory device;   receiving security data, a data operation command for the security data, and an address corresponding to a security region of a memory cell array;   responsive to the guard key being consistent with the received input password, performing a data operation on the security data based on the data operation command and the address; and   responsive to the guard key being inconsistent with the received input password, limiting the data operation for the security data.   
     
     
         15 . The method according to  claim 14 , further comprising:
 responsive to the guard key being inconsistent with the received input password, outputting an alert signal external to the memory device.   
     
     
         16 . The method according to  claim 14 , further comprising:
 receiving a write command in a memory region allocation phase;   receiving a physical address;   generating region information about the security region based on the received physical address; and   storing the generated region information in a first memory in the memory device.   
     
     
         17 . The method according to  claim 16 , wherein the region information comprises a start address corresponding to the security region and a size of the security region, or comprises a start address and an end address corresponding to the security region. 
     
     
         18 . A memory device comprising:
 a memory cell array comprising a first memory region, in which non-secured data is stored, and a second memory region, in which security data is stored; and   a security management circuit configured to store a guard key, receive an input password, and control the memory device such that, responsive to receiving a data operation command for the second memory region, the memory device is configured to perform a data operation on the second memory region responsive to the input password being consistent with the guard key.   
     
     
         19 . The memory device according to  claim 18 , wherein the security management circuit is configured to:
 in a memory region allocation phase, receive a write command and a physical address and store region information about the second memory region based on the received physical address; and   in a data operation phase, determine that the data operation command for the second memory region is a command corresponding to the second memory region by comparing the region information with an address received together with the data operation command for the second memory region.   
     
     
         20 . The memory device according to  claim 18 , wherein, responsive to the input password being inconsistent with the guard key, the security management circuit is configured to control the memory device such that the memory device does not perform the data operation on the second memory region, and to output an alert signal external to the memory device.