Direct bonded copper semiconductor packages and related methods

Abstract

A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.

What is claimed is: 
     
         1 . A power semiconductor package, comprising:
 a first substrate comprising a plurality of connection traces formed in a metal layer of the first substrate;   a die comprising a first face coupled to one of the connection traces of the metal layer of the first substrate;   a second substrate comprising a plurality of connection traces formed in a metal layer of the second substrate; and   a plurality of pins, each terminal pin coupled to one of the connection traces of the metal layer of the first substrate, wherein the plurality of pins extend substantially perpendicularly from the metal layer of the first substrate.   
     
     
         2 . The power semiconductor package of  claim 1 , further comprising a silicone gel encapsulating compound filling a cavity between the metal layer of the first substrate and the metal layer of the second substrate. 
     
     
         3 . The power semiconductor package of  claim 1 , wherein a second face of the die is coupled to one of the connection traces of the plurality of connection traces of the metal layer of the second substrate. 
     
     
         4 . The power semiconductor package of  claim 1 , wherein the first face of the die is coupled to the metal layer of the first substrate using a sintering paste. 
     
     
         5 . The power semiconductor package of  claim 4 , wherein the sintering paste is a silver sintering paste. 
     
     
         6 . The power semiconductor package of  claim 3 , wherein the second face of the die is coupled to the metal layer of the second substrate using a sintering paste. 
     
     
         7 . The power semiconductor package of  claim 6 , wherein the sintering paste is a silver sintering paste. 
     
     
         8 . The power semiconductor package of  claim 1 , wherein the first substrate is a double-sided substrate comprising a dielectric layer sandwiched between the metal layer and a copper layer of the first substrate. 
     
     
         9 . The power semiconductor package of  claim 1 , wherein the second substrate is a double-sided substrate comprising a dielectric layer sandwiched between the metal layer and a copper layer of the second substrate. 
     
     
         10 . The power semiconductor package of  claim 1 , wherein the power semiconductor package comprises only pins. 
     
     
         11 . A power semiconductor package, comprising:
 a first substrate comprising a plurality of connection traces on a first face of the first substrate;   a first die comprising a first face coupled to one of the connection traces of the first face of the first substrate; and   a second substrate comprising a plurality of connection traces on a first face of the second substrate and on a second face of the second substrate, wherein a second face of the first die is coupled to one of the connection traces of the first face of the second substrate;   a second die comprising a first face coupled to one of the connection traces of the second face of the second substrate; and   a third substrate comprising a plurality of connection traces on a first face of the third substrate, wherein a second face of the second die is coupled to one of the connection traces of the first face of the third substrate.   
     
     
         12 . The power semiconductor package of  claim 11 , further comprising an encapsulating compound filling a cavity between the first face of the first substrate and the first face of the second substrate, and filling a cavity between the second face of the second substrate and the first face of the third substrate with an encapsulating compound. 
     
     
         13 . The power semiconductor package of  claim 11 , further comprising a third die comprising a first face coupled with one of a plurality of connection traces of a second face of the third substrate. 
     
     
         14 . The power semiconductor package of  claim 11 , wherein the first face and second face of the first die and the first face and second face of the second die is coupled to one of the first substrate, the second substrate, and the third substrate using a sintering paste. 
     
     
         15 . The power semiconductor package of  claim 14 , wherein the sintering paste is a silver sintering paste. 
     
     
         16 . The power semiconductor package of  claim 11 , wherein the first substrate is a double-sided substrate comprising a dielectric layer sandwiched between the metal layer and a copper layer of the first substrate. 
     
     
         17 . The power semiconductor package of  claim 11 , wherein the second substrate is a double-sided substrate comprising a dielectric layer sandwiched between a metal layer and a copper layer of the second substrate. 
     
     
         18 . The power semiconductor package of  claim 11 , wherein the third substrate is a double-sided substrate comprising a dielectric layer sandwiched between a metal layer and a copper layer of the third substrate. 
     
     
         19 . The power semiconductor package of  claim 11 , wherein the power semiconductor package comprises only one or more pins. 
     
     
         20 . A power semiconductor package, comprising:
 a first substrate comprising a plurality of connection traces formed in a metal layer of the first substrate;   a die comprising a first face coupled to one of the connection traces of the metal layer of the first substrate;   a second substrate comprising a plurality of connection traces formed in a metal layer of the second substrate; and   one or more pins, each pin coupled to one of the connection traces of the metal layer of the first substrate, where the one or more pins extend substantially perpendicularly from the metal layer of the first substrate;   wherein a second face of the die is coupled to one of the connection traces of the metal layer of the second substrate.