Semiconductor package structure and semiconductor manufacturing process

Abstract

A semiconductor package structure includes a semiconductor die, at least one wiring structure, a metal support, a passive element, a plurality of signal vias, and a plurality of thermal structures. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The metal support is used for supporting the semiconductor die. The passive element is electrically connected to the semiconductor die. The signal vias are electrically connecting the passive element and the semiconductor die. The thermal structures are connected to the passive element, and the thermal structures are disposed on a periphery of the at least one wiring structure.

What is claimed is: 
     
         1 . A semiconductor package structure, comprising:
 a semiconductor die, having an active surface;   at least one wiring structure, electrically connected to the active surface of the semiconductor die;   a metal support, supporting the semiconductor die;   a passive element, electrically connected to the semiconductor die;   a plurality of signal vias, electrically connecting the passive element and the semiconductor die; and   a plurality of thermal structures, connected to the passive element, wherein the thermal structures are disposed on a periphery of the at least one wiring structure.   
     
     
         2 . The semiconductor package structure of  claim 1 , wherein an amount of the thermal structures is larger than ten times an amount of the signal vias. 
     
     
         3 . The semiconductor package structure of  claim 2 , wherein the amount of the thermal structures is larger than sixteen times the amount of the signal vias. 
     
     
         4 . The semiconductor package structure of  claim 1 , wherein the passive element includes two electrodes electrically connected to the signal vias and connected to the thermal structures. 
     
     
         5 . The semiconductor package structure of  claim 1 , wherein the passive element includes two electrodes and two metal pins, the two electrodes are electrically connected to the signal vias, and the two metal pins are connected to the thermal structures. 
     
     
         6 . The semiconductor package structure of  claim 1 , wherein the metal support includes a die pad, a plurality of signal pins, and a plurality of thermal pins, the semiconductor die is disposed on the die pad, the signal pins are electrically connected to the signal vias, the thermal pins are connected to the thermal structures. 
     
     
         7 . The semiconductor package structure of  claim 6 , wherein the signal pins and the thermal pins are isolated from each other. 
     
     
         8 . The semiconductor package structure of  claim 1 , wherein the thermal structures are thermal vias. 
     
     
         9 . The semiconductor package structure of  claim 1 , wherein the thermal structures are metal pillars. 
     
     
         10 . The semiconductor package structure of  claim 1 , wherein a junction temperature of the semiconductor die is less than about 150° C. 
     
     
         11 . The semiconductor package structure of  claim 1 , wherein the at least one wiring structure includes a first circuit layer and a second circuit layer, the first circuit layer is electrically connected to the passive element, the second circuit layer is electrically connected to the signal vias. 
     
     
         12 . A semiconductor package structure, comprising:
 a semiconductor die, having an active surface;   at least one wiring structure, electrically connected to the active surface of the semiconductor die;   a passive element, electrically connected to the semiconductor die;   a plurality of signal vias, electrically connecting the passive element and the semiconductor die; and   a plurality of thermal vias, connected to the passive element, wherein the thermal vias are disposed on a periphery of the at least one wiring structure.   
     
     
         13 . The semiconductor package structure of  claim 12 , wherein an amount of the thermal vias is larger than ten times an amount of the signal vias. 
     
     
         14 . The semiconductor package structure of  claim 12 , further comprising an isolation material surrounding the semiconductor die, wherein the thermal vias penetrate through the isolation material. 
     
     
         15 . A semiconductor manufacturing process, comprising:
 (a) providing a semiconductor package, wherein the semiconductor package includes a semiconductor die, at least one wiring structure, a plurality of signal vias and a plurality of thermal structures, the semiconductor die includes an active surface, the at least one wiring structure is electrically connected to the active surface of the semiconductor die, the signal vias are electrically connected to the semiconductor die, the thermal structures are disposed on a periphery of the at least one wiring structure; and   (b) mounting a passive element on the semiconductor package, wherein the passive element is connected to the signal vias and the thermal structures.   
     
     
         16 . The semiconductor manufacturing process of  claim 15 , wherein (a) comprises:
 (a1) providing a metal support, wherein the metal support includes a die pad, a plurality of signal pins and a plurality of thermal pins;   (a2) mounting the semiconductor die on the die pad; and   (a3) forming the signal vias, the thermal structures, at least one wiring structure and a dielectric layer, wherein the at least one wiring structure is electrically connected to the signal vias, the signal vias are electrically connected to the signal pins, the thermal structures are connected to the thermal pins, the dielectric layer surrounds the semiconductor die.   
     
     
         17 . The semiconductor manufacturing process of  claim 16 , wherein after (a3), the semiconductor manufacturing process further comprises:
 (a4) forming a plurality of first recess portions to expose portion of the dielectric layer and between the signal pins and the thermal pins by etching.   
     
     
         18 . The semiconductor manufacturing process of  claim 17 , wherein after (a3), the semiconductor manufacturing process further comprises:
 (a5) forming a plurality of second recess portions to expose portion of the dielectric layer and between the signal pins and the die pad by etching.   
     
     
         19 . The semiconductor manufacturing process of  claim 15 , wherein (a) comprises:
 (a1) providing a metal support, wherein the metal support includes a die pad and a plurality of signal pins;   (a2) mounting the semiconductor die on the die pad; and   (a3) forming the signal vias, the thermal structures and at least one wiring structure, wherein the at least one wiring structure is electrically connected to the signal vias, the signal vias are electrically connected to the signal pins, the thermal structures are disposed on a periphery of the signal pins.   
     
     
         20 . The semiconductor manufacturing process of  claim 15 , wherein (a) comprises:
 (a1) forming the signal vias, the thermal structures and at least one wiring structure, wherein the at least one wiring structure is electrically connected to the signal vias and the thermal structures;   (a2) mounting the semiconductor die on the at least one wiring structure;   (a3) forming an encapsulant surrounding the semiconductor die; and   (a4) forming a plurality of conductive elements, electrically connecting the passive element and the at least one wiring structure.