Light detecting and ranging (lidar) signal processing circuitry

Abstract

Introduced here are techniques for implementing a comparator-based LIDAR system with improved components, such as an improved high-speed comparator circuit, to acquire depth information from the surroundings of an unmanned moving object (e.g., a UAV). In various embodiments, the LIDAR system includes an amplifier module with different configurations of anti-saturation circuitry. The LIDAR system may further include various feedback control mechanisms for noise interference reduction and timing measurement compensation including, for example, dynamic gain adjustment of the photodetector module, and/or dynamic adjustment of comparators' thresholds. Among other components, the disclosed comparator circuit can provide the LIDAR system with a wide dynamic range, preventing large signal amplification saturation while also providing sufficient magnification of small signals.

1 - 55 . (canceled) 
     
     
         56 . A light detection and ranging system, comprising:
 a light sensing module to detect a pulse light signal and generate a corresponding electronic signal; and   an amplifier module, coupled to the light sensing module, to process the corresponding electronic signal, wherein the amplifier module includes an operational amplifier and anti-saturation circuitry coupled to the operational amplifier, wherein the anti-saturation circuitry includes at least one diode configured to be conductive when a voltage of the corresponding electronic signal exceeds a threshold voltage to selectively reduce a gain of the operational amplifier, or to limit a magnitude of the corresponding electronic signal that the operational amplifier receives, or both.   
     
     
         57 . The system of  claim 56 , wherein the anti-saturation circuitry further comprises a diode configured to be conductive when an output signal of the amplifier module exceeds a voltage threshold. 
     
     
         58 . The system of  claim 56 , wherein the anti-saturation circuitry comprises at least one diode connected in parallel with a resistor. 
     
     
         59 . The system of  claim 56 , wherein the anti-saturation circuitry comprises an operational amplifier anti-saturation circuit positioned on a feedback path of the operational amplifier and configured to reduce the gain of the operational amplifier when a diode in the operational amplifier anti-saturation circuit is conducting. 
     
     
         60 . The system of  claim 59 , wherein the operational amplifier anti-saturation circuit is configured such that as the magnitude of the corresponding electronic signal increases, the gain of the operational amplifier is reduced. 
     
     
         61 . The system of  claim 59 , wherein the operational amplifier anti-saturation circuit comprises a diode having first and second terminals, wherein the first terminal of the diode is connected to a first terminal of a first resistor and to an output of the operational amplifier, the second terminal of the diode is connected to a second terminal of the first resistor and to a first terminal of a second resistor, and a second terminal of the second resistor is connected to an input of the operational amplifier. 
     
     
         62 . The system of  claim 56 , wherein the anti-saturation circuitry comprises a pre-amplifier anti-saturation circuit configured to receive the corresponding electronic signal before it is input to the operational amplifier, to limit a magnitude of the corresponding electronic signal that the operational amplifier receives. 
     
     
         63 . The system of  claim 62 , wherein the pre-amplifier anti-saturation circuit includes a diode with a first terminal configured to receive the corresponding electronic signal and a second terminal connected to a reference voltage. 
     
     
         64 . The system of  claim 63 , wherein the pre-amplifier anti-saturation circuit further includes an input resistor that is connected between an input of the amplifier module and an input of the operational amplifier. 
     
     
         65 . The system of  claim 56 , wherein the anti-saturation circuitry further comprises a post-amplifier anti-saturation circuit positioned between an output of the amplifier module and an output of the operational amplifier, to limit a magnitude of an amplified electronic signal that the operational amplifier outputs. 
     
     
         66 . The system of  claim 65 , wherein the post-amplifier anti-saturation circuit includes a diode with a first terminal connected to an output of the amplifier module and a second terminal connected to a reference voltage. 
     
     
         67 . The system of  claim 66 , wherein the post-amplifier anti-saturation circuit further includes an output resistor that is connected between an output of the amplifier module and an output of the operational amplifier. 
     
     
         68 . The system of  claim 56 , further comprising:
 a pulse information acquisition subsystem to extract pulse information based on the corresponding electronic signal; and   a controller having an input to receive the pulse information and configured to compensate for a timing error based on the pulse information.   
     
     
         69 . The system of  claim 68 , wherein the pulse information includes pulse energy information, and wherein an amount of the timing error that the controller is configured to compensate is inversely proportional to an amount of energy indicated in the pulse energy information. 
     
     
         70 . The system of  claim 68 , wherein the pulse information acquisition subsystem is to generate the pulse energy information directly based on output from the amplifier module. 
     
     
         71 . The system of  claim 68 , wherein the pulse information acquisition subsystem comprises at least one of an integrator circuit for calculating pulse energy information of a given pulse by performing integration to calculate an area of the given pulse or a peak holding circuit for retaining peak information of a given pulse. 
     
     
         72 . The system of  claim 71 , wherein the peak holding circuit includes a diode that has a first terminal and a second terminal, the first terminal of the diode arranged to receive a signal to be measured, and the second terminal of the diode connected to a capacitor. 
     
     
         73 . The system of  claim 68 , wherein the pulse information acquisition subsystem comprises a pulse expansion circuit for expanding a waveform of a given pulse. 
     
     
         74 . The system of  claim 68 , wherein the controller is further configured to dynamically control one or more operating parameters of the light detection and ranging system based on an amount or a type of noise observed by the controller. 
     
     
         75 . The system of  claim 68 , further comprising a comparator module having one or more comparators, wherein each of the one or more comparators is coupled to the pulse light signal and configured to compare at least one of a leading edge or a trailing edge of the pulse light signal to a respective triggering threshold. 
     
     
         76 . The system of  claim 75 , wherein the comparator module includes at least two comparators with different triggering thresholds. 
     
     
         77 . The system of  claim 75 , further comprising a time-to-digital converter (TDC) module having one or more TDC circuits, wherein each TDC circuit is coupled to a corresponding comparator in the comparator module and is configured to convert an output from its corresponding comparator into a pulse timing information for the pulse light signal. 
     
     
         78 . The system of  claim 77 , wherein each TDC circuit is configured to perform double-edge timing measurements based on an output signal generated by the corresponding comparator coupled to that TDC circuit. 
     
     
         79 . The system of  claim 77 , wherein the controller is configured to determine timing information for the pulse light signal using double-edge timing measurements received from a plurality of TDC circuits in the TDC module. 
     
     
         80 . The system of  claim 79 , wherein the plurality of TDC circuits includes at least two TDC circuits coupled to corresponding comparators with different triggering thresholds.