Semiconductor device
Abstract
A semiconductor device according to embodiments includes, a SiC substrate, SiC layer, a trench having a side face and a bottom face, a first conductivity type first SiC region, a second conductivity type second SiC region between the first SiC region and the SiC substrate, a first conductivity type third SiC region between the second SiC region and the SiC substrate, a boundary between the second SiC region and the third SiC region provided at a side of the side face, the boundary including a first region, a distance between the first region and a front face of the SiC layer increasing as a distance from the side face to the first region increasing, and distance from the side face to the first region being 0 μm or more and 0.3 μm or less, a gate insulating film and gate insulating film.
Claims
exact text as granted — not AI-modified1 . A semiconductor device, comprising:
a SiC substrate; a SiC layer provided on the SiC substrate, the SiC layer including a first trench and a second trench at a side of front face of the SiC layer, the first trench including a side face and a first bottom face, the second trench including a second bottom face; a first conductivity type first SiC region provided in the SiC layer, the first SiC region is provided between the first trench and the second trench; a second conductivity type second SiC region provided between the first SiC region and the SiC substrate in the SiC layer; a first conductivity type third SiC region provided between the second SiC region and the SiC substrate in the SiC layer, a boundary between the second SiC region and the third SiC region disposed at a side of the side face of the first trench, the boundary including a first region, a distance between the first region and the front face of the SiC layer increasing as a distance from the side face of the first trench to the first region increasing, a distance between the side face of the first trench to an end of the first region close to the first trench being 0 μm or more and 0.3 μm or less; a gate insulating film provided on the side face and the first bottom face of the first trench; a gate electrode, the gate insulating film disposed between the gate electrode and the first SiC region, the second SiC region, and the third SiC region; a first electrode, at least a part of the first electrode disposed in the second trench; and a second electrode, the SiC layer and the SiC substrate provided between the first electrode and the second electrode, wherein a minimum distance between the second electrode and the first trench is larger than a minimum distance between the second electrode and the second SiC region, a first distance along the side face of the first trench is larger than one half of a second distance along the side face of the first trench, the first distance being a distance between a virtual plane parallel to the front face and the second SiC region, the virtual plane including an end of the gate electrode at a side of the first bottom face, the second distance being a distance between the third SiC region and the first SiC region.
2 . The device according to claim 1 , wherein the first region contacts with the side face of the first trench.
3 . The device according to claim 1 , wherein the boundary includes a second region substantially parallel to the front face of the SiC layer, the second region is provided between the first region and the first trench, and the second region contacts with the side face of the first trench.
4 . The device according to claim 1 , wherein the first region has a first inclination angle with respect to the front face, and the first inclination angle is 15° or more and 70° or less.
5 . The device according to claim 1 , wherein the first region has a first inclination angle with respect to the front face, and the first inclination angle is 15° or more and 60° or less.
6 . The device according to claim 1 , wherein the boundary includes a third region substantially parallel to the front face, and the first region is provided between the third region and the first trench.
7 . The device according to claim 1 , wherein the boundary includes a fourth region substantially perpendicular to the front face, and the first region is provided between the fourth region and the first trench.
8 . The device according to claim 1 , wherein the gate insulating film is an oxide film.
9 . The device according to claim 1 , wherein a film thickness of the gate insulating film on the first bottom face of the first trench is thicker than a film thickness of the gate insulating film on the side face of the first trench.
10 . (canceled)
11 . The device according to claim 1 , further comprising a second conductivity type fifth SiC region provided between the first bottom face of the first trench and the third SiC region in the SiC layer, the fifth SiC region being in contact with the first bottom face.
12 . (canceled)
13 . The device according to claim 1 , further comprising a second conductivity type fourth SiC region provided between the second bottom face of the second trench and the second SiC region in the SiC layer, the fourth SiC region having higher second conductivity type impurity concentration than that of the second SiC region.
14 . The device according to claim 1 , wherein an interior angle of the second SiC region at the boundary is 90° or more.
15 . The device according to claim 1 , wherein the boundary does not includes a bending portion with an angle of 90° or less.
16 . The device according to claim 1 , wherein the first conductivity type is an n-type.
17 . The device according to claim 1 , wherein the SiC substrate is a first conductivity type.
18 . The device according to claim 1 , wherein the SiC substrate is a second conductivity type.
19 . A semiconductor device, comprising:
a SiC substrate; a SiC layer provided on the SiC substrate, the SiC layer including a first trench and a second trench at a side of front face of the SiC layer, the first trench including a side face and a first bottom face, the second trench including a second bottom face; a first conductivity type first SiC region provided in the SiC layer, the first SiC region is provided between the first trench and the second trench; a second conductivity type second SiC region provided between the first SiC region and the SiC substrate in the SiC layer; a first conductivity type third SiC region provided between the second SiC region and the SiC substrate in the SiC layer, a boundary between the second SiC region and the third SiC region disposed at a side of the side face of the first trench, the boundary including a first region, the first region having a first position and a second position, the first position being closer to the first trench than the second position, a distance between the second position and the front face of the SiC layer being larger than a distance between the first position and the front face of the SiC layer, a distance between the side face of the first trench to an end of the first region close to the first trench being 0 μm or more and 0.3 μm or less; a gate insulating film provided on the side face and the first bottom face of the first trench; a gate electrode, the gate insulating film disposed between the gate electrode and the first SiC region, the second SiC region, and the third SiC region; a first electrode, at least a part of the first electrode disposed in the second trench; and a second electrode, the SiC layer and the SiC substrate provided between the first electrode and the second electrode, wherein a minimum distance between the second electrode and the first trench is larger than a minimum distance between the second electrode and the second SiC region, a first distance along the side face of the first trench is larger than one half of a second distance along the side face of the first trench, the first distance being a distance between a virtual plane parallel to the front face and the second SiC region, the virtual plane including an end of the gate electrode at a side of the first bottom face, the second distance being a distance between the third SiC region and the first SiC region.
20 . A semiconductor device, comprising:
a SiC substrate; a SiC layer provided on the SiC substrate, the SiC layer including a first trench and a second trench at a side of front face of the SiC layer, the first trench including a side face and a first bottom face, the second trench including a second bottom face; a first conductivity type first SiC region provided in the SiC layer, the first SiC region is provided between the first trench and the second trench; a second conductivity type second SiC region provided between the first SiC region and the SiC substrate in the SiC layer; a first conductivity type third SiC region provided between the second SiC region and the SiC substrate in the SiC layer, a boundary between the second SiC region and the third SiC region disposed at a side of the side face of the first trench, the boundary including a first region, the first region having a first position and a second position, the first position being closer to the first trench than the second position, a distance between the second position and a back face of the SiC substrate being smaller than a distance between the first position and the back face of the SiC substrate, a distance between the side face of the first trench to an end of the first region close to the first trench being 0 μm or more and 0.3 μm or less; a gate insulating film provided on the side face and the first bottom face of the first trench; a gate electrode, the gate insulating film disposed between the gate electrode and the first SiC region, the second SiC region, and the third SiC region; a first electrode, at least a part of the first electrode disposed in the second trench; and a second electrode, the SiC layer and the SiC substrate provided between the first electrode and the second electrode, wherein a minimum distance between the second electrode and the first trench is larger than a minimum distance between the second electrode and the second SiC region, a first distance along the side face of the first trench is larger than one half of a second distance along the side face of the first trench, the first distance being a distance between a virtual plane parallel to the front face and the second SiC region, the virtual plane including an end of the gate electrode at a side of the first bottom face, the second distance being a distance between the third SiC region and the first SiC region.
21 . The device according to claim 1 , wherein a distance between the front face to the second bottom face is larger than one half of a distance between the front face to the first bottom face.Join the waitlist — get patent alerts
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