Vertical memory devices

Abstract

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes gate layers and insulating layers that are stacked alternatingly along a first direction perpendicular to a substrate of the semiconductor device in a first region upon the substrate. The gate layers and the insulating layers are stacked of a stair-step form in a second region. The semiconductor device includes a channel structure that is disposed in the first region. The channel structure and the gate layers form a stack of transistors in a series configuration with the gate layers being gates for the transistors. The semiconductor device includes a contact structure disposed in the second region, and a first dummy channel structure disposed in the second region and around the contact structure. The first dummy channel structure is patterned with a first shape that is different from a second shape of the channel structure.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 gate layers and insulating layers that are stacked alternatingly along a first direction perpendicular to a substrate of the semiconductor device in a first region upon the substrate, wherein the gate layers and the insulating layers are stacked of a stair-step form in a second region upon the substrate;   a channel structure that is disposed in the first region and extends in the first direction, wherein the channel structure is through the gate layers and the insulating layers, and the channel structure and the gate layers form a stack of transistors in a series configuration with the gate layers being gates for the transistors;   a contact structure disposed in the second region to form a conductive connection with one of the gate layers; and   a first dummy channel structure disposed in the second region and around the contact structure, the first dummy channel structure being patterned with a first shape that is different from a second shape of the channel structure.   
     
     
         2 . The semiconductor device of  claim 1 , wherein:
 the channel structure has a circular shape at a horizontal cross-section of the semiconductor device; and   the first dummy channel structure has a non-circular shape at the horizontal cross-section.   
     
     
         3 . The semiconductor device of  claim 2 , wherein:
 the first dummy channel structure has the non-circular shape that is adjustable by two or more parameters that define the non-circular shape.   
     
     
         4 . The semiconductor device of  claim 3 , wherein
 the first dummy channel structure has at least one of a capsule shape, a rectangular shape, and an arc shape.   
     
     
         5 . The semiconductor device of  claim 1 , further comprising:
 a second dummy channel structure that is disposed to be symmetric to the first dummy channel structure with regard to the contact structure.   
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 multiple dummy channel structures that are disposed around the contact structure in a non-symmetric configuration with regard to the contact structure.   
     
     
         7 . The semiconductor device of  claim 1 , further comprising:
 multiple dummy channel structures that are disposed around the contact structure, a maximum distance between the multiple dummy channel structures being shorter than a first limit.   
     
     
         8 . The semiconductor device of  claim 1 , wherein:
 the first dummy channel structure is formed of same materials as the channel structure.   
     
     
         9 . The semiconductor device of  claim 1 , wherein
 the first dummy channel structure is formed of silicon dioxide.   
     
     
         10 . The semiconductor device of  claim 1 , further comprising:
 a gate line slit that extends in the stack of the gate layers and the insulating layers, a maximum distance between the gate line slit and the first dummy channel structure being shorter than a second limit.   
     
     
         11 . A method, comprising:
 characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial layers and insulating layers upon a substrate of a semiconductor device, the channel holes being in a core region and the dummy channel holes being in a staircase region, the stack of alternating sacrificial gate layers and insulating layers extending from the core region into in the staircase region of a stair-step form; and   determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process, the first shape being different from a second shape for defining the channel holes.   
     
     
         12 . The method of  claim 11 , further comprising:
 generating the layout for the semiconductor device, the layout having first instances of the first shape in a first area of the layout corresponding to the staircase region, and having second instances of the second shape in a second area of the layout corresponding to the core region.   
     
     
         13 . The method of  claim 11 , further comprising:
 determining a non-circular shape for the dummy channel holes that is different from a circle shape of the channel holes.   
     
     
         14 . The method of  claim 13 , further comprising:
 adjusting two or more parameters that define the non-circular shape based on the characterization of the etch process.   
     
     
         15 . The method of  claim 13 , further comprising:
 selecting the non-circular shape from at least a capsule shape, a bar shape, and an arc shape.   
     
     
         16 . The method of  claim 12 , further comprising:
 disposing, in the layout, a first instance and a second instance of the first shape that are symmetric with regard to a pattern that defines a contact in the staircase region.   
     
     
         17 . The method of  claim 12 , further comprising:
 disposing multiple instances corresponding to the dummy channel holes that are in a non-symmetric configuration with regard to a contact in the staircase region.   
     
     
         18 . The method of  claim 12 , further comprising:
 disposing multiple instances corresponding to the dummy channel holes, a maximum distance between the multiple instances being shorter than a first limit.   
     
     
         19 . The method of  claim 12 , further comprising:
 generating a mask layer in the layout to differentiate the core region and the staircase region, the mask layer being used to form first dummy channel structures corresponding to the first dummy channel holes in the staircase region with different materials from channel structures corresponding to the channel holes in the core region.   
     
     
         20 . The method of  claim 12 , further comprising:
 generating a pattern in the layout for defining a gate line slit in the semiconductor device, a maximum distance between the pattern and the first instances being shorter than a second limit.