Semiconductor package and method of manufacturing the semiconductor package

Abstract

A semiconductor package includes a mold substrate, at least one first semiconductor chip in the mold substrate and including chip pads, wiring bonding pads formed at a first surface of the mold substrate and connected to the chip pads by bonding wires, and a redistribution wiring layer covering the first surface of the mold substrate and including redistribution wirings connected to the wiring bonding wirings.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a mold substrate;   a first semiconductor chip, a support member and a plurality of second semiconductor chips in the mold substrate, the first semiconductor chip including first chips pads, the second semiconductor chip including second chip pads;   wiring bonding pads at a first surface of the mold substrate, the wiring bonding pads connected to the first chip pads and the second chip pads by bonding wires, at least a portion of each of the wiring bonding pads embedded within the mold substrate; and   a redistribution wiring layer covering the first surface of the mold substrate, the redistribution wiring layer including redistribution wirings, the redistribution wirings connected to the wiring bonding pads,   wherein at least a portion of the first semiconductor chip and at least a portion of the support member are exposed from the first surface of the mold substrate such that the at least a portion of the first semiconductor chip and the at least a portion of the support member are in contact with the redistribution wiring layer, and   wherein the plurality of second semiconductor chips are stacked on the first semiconductor chip and the support member in the mold substrate.   
     
     
         2 . The semiconductor package of  claim 1 , wherein a thickness of the first semiconductor chip is the same as a thickness of the support member. 
     
     
         3 . The semiconductor package of  claim 1 , wherein the second semiconductor chips are mounted on the first semiconductor chip and the support member using an adhesive film that is in contact with the first semiconductor chip and the support member. 
     
     
         4 . The semiconductor package of  claim 1 , wherein the first semiconductor chip and the support member are arranged on the redistribution wiring layer to be spaced apart from each other. 
     
     
         5 . The semiconductor package of  claim 1 , wherein the redistribution wiring layer comprises a first insulation layer, which is on the first surface of the mold substrate and includes openings exposing the wiring bonding pads. 
     
     
         6 . The semiconductor package of  claim 1 , wherein the first chip pads are on a third surface of the first semiconductor chip and a fourth surface of the first semiconductor chip opposite to the first surface is in contact with the redistribution wiring layer. 
     
     
         7 . The semiconductor package of  claim 6 , wherein the fourth surface of the first semiconductor chip is exposed from the first surface of the mold substrate. 
     
     
         8 . The semiconductor package of  claim 6 , wherein a fifth surface of the support member is in contact with the redistribution wiring layer and the fifth surface of the support member is exposed from the first surface of the mold substrate. 
     
     
         9 . The semiconductor package of  claim 8 , wherein the fourth surface of the first semiconductor chip and the fifth surface of the support member are coplanar with the redistribution wiring layer. 
     
     
         10 . The semiconductor package of  claim 1 , wherein a seventh surface of each of the wiring bonding pads is exposed from the first surface of the mold substrate, and each of the bonding wires is bonded to an eighth surface of each of the wiring bonding pads opposite to the seventh surface. 
     
     
         11 . A semiconductor package, comprising:
 a redistribution wiring layer including redistribution wirings and fan out type landing pads connected to the redistribution wirings, the redistribution wiring layer having a first surface and a second surface that are opposite to each other;   a first semiconductor chip on the first surface of the redistribution wiring layer, the first semiconductor chip including a third surface having first chip pads thereon and a fourth surface facing the redistribution wiring layer and opposite to the third surface;   a support member on the first surface of the redistribution wiring layer to be spaced apart from the first semiconductor chip;   a plurality of second semiconductor chips stacked on the first semiconductor chip and the support member;   wiring bonding pads at the first surface of the redistribution wiring layer such that a fifth surface of each of the wiring bonding pads is above the redistribution wiring layer, and a sixth surface of each of the wiring bonding pads opposite to the fifth surface is coplanar with the first surface of the redistribution wiring layer, the wiring bonding pads connected to corresponding ones of the redistribution wirings;   bonding wires connecting the first chip pads with the wiring boding pads such that the first chip pads are connected to corresponding ones of the fan out type landing pads on the second surface of the redistribution wiring layer; and   a mold substrate on the redistribution wiring layer, the mold substrate covering the first semiconductor chip, the support member, the second semiconductor chips, the wiring bonding pads and the bonding wires such that at least a portion of the first semiconductor chip and at least a portion of the support member are exposed from a seventh surface of the mold substrate that faces the first surface of the redistribution wiring layer.   
     
     
         12 . The semiconductor package of  claim 11 , wherein the at least a portion of the first semiconductor chip and the at least a portion of the support member are in contact with the first surface of the redistribution wiring layer. 
     
     
         13 . The semiconductor package of  claim 11 , wherein the wiring bonding pads are on the first surface of the redistribution wiring layer. 
     
     
         14 . The semiconductor package of  claim 11 , wherein a thickness of the first semiconductor chip is the same as a thickness of the support member. 
     
     
         15 . The semiconductor package of  claim 11 , wherein the second semiconductor chips are mounted on the first semiconductor chip and the support member using an adhesive film that is in contact with the first semiconductor chip and the support member. 
     
     
         16 . The semiconductor package of  claim 11 , wherein the first semiconductor chip and the support member are arranged on the redistribution wiring layer to be spaced apart from each other. 
     
     
         17 . The semiconductor package of  claim 11 , wherein the redistribution wiring layer comprises a first insulation layer, which is on the seventh surface of the mold substrate and includes openings exposing the wiring bonding pads. 
     
     
         18 . The semiconductor package of  claim 11 , wherein the fourth surface of the first semiconductor chip is in contact with the first surface of the redistribution wiring layer. 
     
     
         19 . The semiconductor package of  claim 18 , wherein the fourth surface of the first semiconductor chip is exposed from the seventh surface of the mold substrate. 
     
     
         20 . The semiconductor package of  claim 19 , wherein a ninth surface of the support member is in contact with the first surface of the redistribution wiring layer and the ninth surface of the support member is exposed from the seventh surface of the mold substrate.