Methods and systems for system design automation (sda) of mixed signal electronic circuitry including embedded software designs

Abstract

Methods and systems for SDA of mixed signal electronic circuitry including embedded software designs for creating ASICs, sub-systems, and SoCs. The SDA system described extends IP reuse beyond the circuit and stand-alone verification capabilities that are common practice today which limit the benefits of reuse. By solving the integration problem first in a loosely coupled manner, complex mixed signal SoC devices may achieve higher levels of IP reuse with push button ease through the cloud, significantly improving time to market, design resource limitations, risks for first time silicon success, and the tasks of managing business multiple relationships of IP providers. SDA generated designs use a multi-agent method of operation, creating powerful and flexible designs that provide both NOC (Network on a Chip) and NBC (Network Beyond the Chip) for distributed system operation, and enhanced non-intrusive in-system monitoring for mission critical and safety related applications.

We claim: 
     
         1 . A system,
 comprising, a plurality of integration components for the functional integration of a plurality of digital, analog, and/or software Intellectual Property (IP) functions through configuration settings where the IP functions remain autonomous and loosely coupled;   data output values including source identifer information and data inputs with a plurality of data input sink selections to provide configurable data routing.   
     
     
         2 . The system of  claim 1 , further comprising instructions for providing both hardware and software IP sockets suitable for IP functions to be interchangably represented in either a hardware or software form. 
     
     
         3 . The system of  claim 1 , further comprising instructions for generating system components for collecting wire event outputs from said IP sockets with selection controls for distributed use of wire event inputs to said IP sockets. 
     
     
         4 . The system of  claim 1 , further comprising of generating system components for providing clock, reset, and/or power management control of IP sockets. 
     
     
         5 . The system of  claim 1 , further comprising of generating system component for providing IP socket monitors and stimulus accessible with a debug port. 
     
     
         6 . The system of  claim 1 , further comprising of mode control configuration control for providing the integration control of IP inputs and outputs. 
     
     
         7 . The system of  claim 1 , further comprising of enable features for dynamically changing the operational makeup of the system during operation. 
     
     
         8 . The system of  claim 1 , further comprising of bridge and/or interface hardware that provides unlimited configurable extensibility between IP functions between subsystems within and/or beyond a chip. 
     
     
         9 . The system of  claim 1 , further comprising of customizable integration fabric without requiring changes to the IP modules used. 
     
     
         10 . A method, comprising the steps of:
 providing a web browser accessible dashboard for system design stakeholders according to their project roles;   providing a web browser tool interface for entering information defining an IP function, interface, and access control information to provide a container for importing the design information relating to the IP;   providing a web browser dashboard that provides a consolidated IP marketing and support site for IP owners; and   providing a web browser dashboard that provides a consolidated IP licensing management site for IP customers.   
     
     
         11 . The method of  claim 10 , further comprising the step of providing of a web browser accessible database catalog of SDA-ready IP. 
     
     
         12 . The method of  claim 10 , further comprising the step of providing a web browser tool interface for selecting and configuring IP modules, and defining acceess control for SDA functional integration of a system. 
     
     
         13 . The method of  claim 10 , further comprising the step of providing of a web browser accessible simulation of a compiled SDA generated design and test bench. 
     
     
         14 . The method of  claim 10 , further comprising the step of providing a web browser accessible FPGA emulation of a compiled SDA generated design and test bench. 
     
     
         15 . A method for system design automation (SDA) of mixed signal electronic circuitry and software, comprising the steps of:
 generating a networked plurality of mixed signal circuitry and software sockets for instantiating from system integration database entries for mixed signal circuitry and software functional IP module blocks, further comprising the steps of:   presenting event wire and communication data outputs of hardware and software functional IP with identifiers according to output web-accessible interface;   implementing configurable input select control circuitry and/or software for providing inputs of hardware and software functional IP using event wire and communication data output identifiers according to a web-accessible interface;   implementing configurable mode control registers, memory contents, and/or parameters for providing functional IP module block functional modifiers according to mode web-accessible interface;   assembling said mixed signal circuitry and software wrappers into an SDA generated design using a combination of network on a chip and/or software operating system and/or network beyond a chip to allow functional IP modules to operate together as a system;   organizing and storing said mixed signal circuitry and software IP module design files into IP containers; and   accessing said IP containers using a predetermined version control software system; and   providing said IP including test bench and verification components for providing stimulus and monitoring IP functionality during operation.   
     
     
         16 . The method of  claim 15 , further comprising the step of a generated primary first system and a second test bench system for functionally verifying IP included in primary first system. 
     
     
         17 . The method of  claim 15 , further comprising of the step of providing said IP including test bench and verification components for providing stimulus and monitoring IP functionality during operation. 
     
     
         18 . The method of  claim 15 , further comprising the step of a generated primary first system and a second test bench system for functionally verifying IP included in primary first system. 
     
     
         19 . The method of  claim 15 , further comprising the step of emulating both generated systems within a FPGA for functional real-time validation. 
     
     
         20 . The method of  claim 15 , further comprising the step of universal driver software to interface to SDA generated designs using loosely coupled configurable data routing.