Semiconductor device, solid state imaging element, and electronic apparatus

Abstract

The present disclosure relates to a semiconductor device, a solid state imaging element, and an electronic apparatus in which the adverse effect due to hot carrier luminescence can be suppressed. In them, an element formation unit in which a plurality of elements are formed and an interconnection unit in which interconnections connecting elements are formed are stacked. A structure object formed between a light receiving element that receives light and performs photoelectric conversion and an active element that forms a peripheral circuit placed around the light receiving element in such a manner that the gap in the thickness direction of the element formation unit is not more than a prescribed spacing and formed of a material that inhibits the propagation of light is placed in the element formation unit. The present technology can be applied to a back-side illumination solid state imaging element, for example.

1 - 26 . (canceled) 
     
     
         27 . A semiconductor device comprising:
 a first substrate; and   a second substrate stacked on the first substrate, wherein the first substrate comprises:
 a pixel region including an array of a plurality of light receiving elements configured to receive light through a first surface of the first substrate and perform photoelectric conversion; 
 a peripheral region outside of and surrounding the array of the plurality of light receiving elements in the pixel region, the peripheral region including a transistor that forms part of a peripheral circuit that drives circuitry in the pixel region; and 
 a shield disposed between the peripheral region and the pixel region so as to surround the pixel region in a plan view, wherein the shield is disposed in the first substrate such that a gap exists between a tip of the shield and a second surface of the first substrate in a thickness direction of the first substrate, wherein the gap is less than 400 nm, and wherein the second surface is opposite the first surface. 
   
     
     
         28 . The semiconductor device of  claim 27 , wherein the array of the plurality of light receiving elements are disposed in the second surface of the first substrate. 
     
     
         29 . The semiconductor device of  claim 27 , wherein the transistor includes a gate electrode disposed in the second substrate and a source/drain disposed in the second surface of the first substrate. 
     
     
         30 . The semiconductor device of  claim 29 , wherein the first substrate includes:
 a first isolation structure disposed in the second surface, adjacent to the drain, and including a third surface that is coplanar with the second surface.   
     
     
         31 . The semiconductor device of  claim 30 , a second isolation structure disposed in the second surface, adjacent to the source, and including a fourth surface that is coplanar with the second surface, wherein the first and second isolation structures are positioned so that the transistor is electrically isolated from other transistors, and wherein the first and second isolation structures are formed to a depth in the first substrate that is less than a depth of the shield. 
     
     
         32 . The semiconductor device according to  claim 31 , wherein the first isolation structure touches the drain, wherein the second substrate is stacked on the second surface of the first substrate such that, in the plan view, interconnections in the second substrate overlap with the pixel region, the transistor, and the shield. 
     
     
         33 . The semiconductor device according to  claim 32 , wherein the interconnections are electrically connected to the peripheral circuit and carry signals that drive the peripheral circuit. 
     
     
         34 . The semiconductor device according to  claim 27 , wherein the shield is a unitary structure that extends from the second surface toward the first surface and is formed of a material having a different permittivity than the first substrate. 
     
     
         35 . The semiconductor device of  claim 27 , wherein the first substrate includes a silicon substrate. 
     
     
         36 . The semiconductor device according to  claim 27 , further comprising:
 a support substrate joined to the second substrate and configured to support the first substrate and the second substrate.   
     
     
         37 . The semiconductor device according to  claim 27 , further comprising:
 a lens layer including curved portions disposed over the pixel region and a flat portion disposed over the peripheral region.   
     
     
         38 . The semiconductor device according to  claim 27 , wherein the shield is formed of a material that refracts or absorbs hot carrier luminescence from the transistor. 
     
     
         39 . The semiconductor device according to  claim 27 , wherein a sidewall of the shield is inclined. 
     
     
         40 . The semiconductor device according to  claim 27 , wherein the shield is formed of a metal that reflects light. 
     
     
         41 . The semiconductor device according to  claim 27 , further comprising an insulator surrounding a periphery of the shield. 
     
     
         42 . The semiconductor device according to  claim 27 , further comprising an electrode for extracting an electric potential of the shield. 
     
     
         43 . The semiconductor device according to  claim 27 , wherein the pixel region includes an analog element with high sensitivity to light noise. 
     
     
         44 . The semiconductor device according to  claim 27 , wherein the shield is formed of a material that reflects or absorbs infrared light in the first substrate. 
     
     
         45 . The semiconductor device according to  claim 27 , further comprising a second shield formed between the pixel region and the shield, wherein there is no pixel region between the shield and the second shield.