Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges

Abstract

A system and method for efficiently storing and driving data between pipeline stages. In various embodiments, a flip-flop circuit includes a bypass circuit, which is a tri-state inverter, and the bypass circuit receives a clock signal and a version of a data signal. When the clock signal received by the flip-flop circuit is asserted, the output of the bypass circuit is sent as the output of the flip-flop circuit. In one example, the version of the data signal received by the bypass circuit is the data signal. In another example, the version of the data signal received by the bypass circuit is the output of a master latch. Although the output of the master latch is pre-charged, when the clock is asserted, each of a late arriving rising and falling data transition are included in the critical path of the flip-flop circuit.

1 . An apparatus comprising:
 a data input stage of a sequential element configured to receive a data signal;   a shadow latch configured to receive only an output of the data input stage and a clock signal; and   a bypass circuit configured to receive the clock signal and a version of the data signal; and   in response to determining the clock signal is asserted:
 send the output of the data input stage to the shadow latch; 
 prevent sending an output of the shadow latch as an output of the apparatus; and 
 send an output of the bypass circuit as the output of the apparatus. 
   
     
     
         2 . The apparatus as recited in  claim 1 , wherein the version of the data signal received by the bypass circuit is the data signal. 
     
     
         3 . The apparatus as recited in  claim 2 , wherein the output of the bypass circuit is an inverted value of the data signal generated by one stage of inversion. 
     
     
         4 . The apparatus as recited in  claim 2 , wherein the data input stage is configured to receive the clock signal. 
     
     
         5 . The apparatus as recited in  claim 4 , wherein the clock signal is a pulse clock signal generated from a source clock signal. 
     
     
         6 . The apparatus as recited in  claim 1 , wherein the version of the data signal received by the bypass circuit is the output of the data input stage, wherein the data input stage is a master latch. 
     
     
         7 . The apparatus as recited in  claim 6 , wherein the output of the bypass circuit is a non-inverted value of the data signal generated by two data input stages of inversion. 
     
     
         8 . The apparatus as recited in  claim 6 , wherein:
 a sequential feedback circuit in the master latch is configured to receive a delayed version of the clock signal; and   a sequential feedback circuit in the shadow latch is configured to receive the clock signal.   
     
     
         9 . A method, comprising:
 receiving, by a data input stage of a sequential element, a data signal;   receiving, by a shadow latch, only an output of the data input stage and a clock signal;   receiving, by a bypass circuit, the clock signal and a version of the data signal;   in response to determining the clock signal is asserted:
 sending the output of the data input stage to the shadow latch; 
 preventing sending an output of the shadow latch as an output of a flip-flop circuit; and 
 sending an output of the bypass circuit as the output of the flip-flop circuit. 
   
     
     
         10 . The method as recited in  claim 9 , wherein the version of the data signal received by the bypass circuit is the data signal. 
     
     
         11 . The method as recited in  claim 10 , wherein the output of the bypass circuit is an inverted value of the data signal generated by one stage of inversion. 
     
     
         12 . The method as recited in  claim 9 , wherein the version of the data signal received by the bypass circuit is the output of the data input stage, wherein the data input stage is a master latch. 
     
     
         13 . The method as recited in  claim 12 , wherein the output of the bypass circuit is a non-inverted value of the data signal generated by two data input stages of inversion. 
     
     
         14 . The method as recited in  claim 12 , further comprising:
 receiving, by a sequential feedback circuit in the master latch, a delayed version of the clock signal; and   receiving, by a sequential feedback circuit in the shadow latch, the clock signal.   
     
     
         15 . A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable by a processor to:
 receive, by a data input stage of a sequential element, a data signal;   receive, by a shadow latch, only an output of the data input stage and a clock signal;   receive, by a bypass circuit, the clock signal and a version of the data signal;   in response to determining the clock signal is asserted:
 send the output of the data input stage to the shadow latch; 
 prevent sending an output of the shadow latch as an output of the flip-flop circuit; and 
 send an output of the bypass circuit as the output of the flip-flop circuit. 
   
     
     
         16 . The non-transitory computer readable storage medium as recited in  claim 15 , wherein the version of the data signal received by the bypass circuit is the data signal. 
     
     
         17 . The non-transitory computer readable storage medium as recited in  claim 16 , wherein the output of the bypass circuit is an inverted value of the data signal generated by one stage of inversion. 
     
     
         18 . The non-transitory computer readable storage medium as recited in  claim 16 , wherein the version of the data signal received by the bypass circuit is the output of the data input stage, wherein the data input stage is a master latch. 
     
     
         19 . The non-transitory computer readable storage medium as recited in  claim 18 , wherein the output of the bypass circuit is a non-inverted value of the data signal generated by two data input stages of inversion. 
     
     
         20 . The non-transitory computer readable storage medium as recited in  claim 18 , wherein the program instructions are executable by a processor to:
 receive, by a sequential feedback circuit in the master latch, a delayed version of the clock signal; and   receive, by a sequential feedback circuit in the shadow latch, the clock signal.