Narrow-mesa super-junction mosfet

Abstract

A transistor device includes an n-doped pillar and a p-doped pillar forming a super-junction structure on a substrate. An isolation structure is disposed in a trench between the n-doped pillar and the p-doped pillar, and a source and a gate are disposed on the n-doped pillar. The isolation structure can include an air gap encapsulated in the trench by an oxide plug. The isolation structure can include an epi liner disposed on surfaces of the n-doped pillar and the p-doped pillar.

1 . A device comprising:
 an n-doped pillar and a p-doped pillar forming a super-junction structure on a substrate, the n-doped pillar and p-doped pillar each having a height perpendicular to the substrate and a lateral width parallel to the substrate, a lateral cross section of the n-doped pillar including a gate and at most one source; and   an isolation structure disposed in a trench between the n-doped pillar and the p-doped pillar.   
     
     
         2 . The device of  claim 1 , wherein the trench has depth in a range of about 30 μm to 50 μm. 
     
     
         3 . The device of  claim 1 , wherein the isolation structure includes an air gap disposed between the n-doped pillar and the p-doped pillar. 
     
     
         4 . The device of  claim 3 , wherein an air gap is filled with a gas at atmospheric or sub-atmospheric pressures. 
     
     
         5 . The device of  claim 1 , wherein an epi liner is disposed between the isolation structure and the n-doped pillar and between the isolation structure and the p-doped pillar. 
     
     
         6 . The device of  claim 5 , wherein the epi liner when first formed is more lightly doped than the n-doped pillar and the p-doped pillar. 
     
     
         7 . The device of  claim 1 , wherein the trench has an opening width at about the tops of the n-doped pillar and the p-doped pillar that is wider than an opening width of the trench in a lower body portion of the trench. 
     
     
         8 . The device of  claim 1 , wherein a top of the n-doped pillar has a rounded shape. 
     
     
         9 . The device of  claim 1 , wherein the isolation structure includes deposited silicon oxide. 
     
     
         10 . The device of  claim 9 , wherein the deposited silicon oxide forms an oxide plug in an upper portion of the trench and encloses an air gap in a lower portion of the trench. 
     
     
         11 . (canceled) 
     
     
         12 . The device of  claim 1 , wherein the gate is disposed in a gate trench etched in the n-doped pillar, the gate trench having a pair of vertical sidewalls formed by material of the n-doped pillar. 
     
     
         13 . A transistor comprising:
 a first mesa stripe of a first conductivity type and a second mesa stripe of a second conductivity type disposed on a semiconductor substrate;   a gate disposed in a gate trench etched in a top of the first mesa stripe, the gate trench having sidewalls formed by material of the first mesa stripe; and   a sequence of source regions disposed on the top of the first mesa stripe at intervals along a length of the first mesa stripe, a first of the sequence of the source regions being disposed on one lateral side of the first mesa stripe and the next of the sequence of the source regions being disposed on an opposite lateral side of the first mesa stripe along the length of the first mesa stripe.   
     
     
         14 . The transistor of  claim 13 , wherein a section of the gate trench is placed off-center on a first side of the top of the first mesa stripe. 
     
     
         15 . The transistor of  claim 14 , wherein the gate trench shifts from the first side to another side of the first mesa stripe along a length of the first mesa stripe. 
     
     
         16 . The transistor of  claim 13 , wherein a lateral cross section of the first mesa stripe perpendicular to the length of the first mesa stripe-includes the gate and at most one source region. 
     
     
         17 . The transistor of  claim 13  wherein the gate trench forms a gate trench loop on the top of the first mesa stripe. 
     
     
         18 . A method, comprising:
 disposing an n-doped column and a p-doped column on a substrate, the n-doped column and the p-doped column each having a respective initial column width and being separated by a trench having an initial trench width;   providing additional semiconductor real estate for fabricating device components in the n-doped column and p-doped column by depositing epitaxial material having an epi thickness on vertical sides of the columns to form an n-doped pillar and a p-doped pillar, the n-doped pillar and the p-doped pillar each having a respective pillar width greater than the respective initial column width, and the trench between the n-doped pillar and a p-doped pillar having a trench width smaller than the initial trench width;   disposing an isolation structure in the trench between the n-doped pillar and the p-doped pillar; and   disposing a source and a gate on the n-doped pillar.   
     
     
         19 . The method of  claim 18 , wherein disposing the isolation structure in the trench between the n-doped pillar and the p-doped pillar includes disposing an oxide plug in the trench between the n-doped pillar and the p-doped pillar, the oxide plug capping the trench and encapsulating an air gap in the trench. 
     
     
         20 . The method of  claim 18 , wherein disposing the isolation structure in the trench between the n-doped pillar and the p-doped pillar includes disposing an epi liner between the isolation structure and the n-doped pillar and between the isolation structure and the p-doped pillar. 
     
     
         21 . The method of  claim 18  wherein the n-doped pillar and the p-doped pillar each have a respective pillar width greater than about 1 micron, and the trench between the n-doped pillar and a p-doped pillar has a trench width smaller than about 0.5 microns.