Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1<H2). By making the surface of the element isolation region STI1 receded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STI2 is not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.

What is claimed is: 
     
         1 . A semiconductor device comprising a nonvolatile memory cell arranged in a first active region in a first region of a semiconductor substrate and an MISFET arranged in a second active region in a second region,
 wherein the nonvolatile memory cell comprises:   a first gate electrode part arranged above the semiconductor substrate;   a second gate electrode part arranged above the semiconductor substrate so as to be adjacent to the first gate electrode part;   a first insulating film formed between the first gate electrode part and the semiconductor substrate, and   a second insulating film formed between the second gate electrode part and the semiconductor substrate and between the first gate electrode part and the second gate electrode part and having therein a charge accumulation part,   wherein the MISFET comprises:   a third gate electrode part arranged above the semiconductor substrate and including a metal film or a metal compound film;   a third insulating film formed between the first gate electrode part and the semiconductor substrate and including a high-dielectric-constant film; and   source and drain regions formed in the semiconductor substrate on both sides of the third gate electrode part, and   wherein the surface of a first element isolation region surrounding the first active region in the first region is lower than the surface of a second element isolation region surrounding the second active region in the second region.