Indium gallium arsenide metal oxide semiconductor field effect transistor having a low contact resistance to metal electrode

Abstract

A semiconductor device that includes source and drain regions that are doped to an n-type conductivity and are comprised of a type III-V semiconductor material. The semiconductor device further includes a contact to at least one of the source and drain regions. The contact includes an interface passivation layer atop the at least one source and drain region, and an n-type zinc oxide layer. A conduction band of the type III-V semiconductor material of the at least one source and drain region is substantially aligned with a conduction band of the n-type zinc oxide containing layer.

What is claimed is: 
     
         1 . A method of forming a semiconductor device comprising:
 providing a field effect transistor including a region composed of a type III-V semiconductor material;   forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface of the at least one of the type III-V semiconductor material to provide a passivated surface;   forming a metal oxide containing layer on the passivated surface; and   forming a metal contact on the metal oxide containing layer.   
     
     
         2 . The method of  claim 1 , wherein the type III-V semiconductor material is indium gallium arsenide (InGaAs). 
     
     
         3 . The method of  claim 1 , wherein a channel region of the field effect transistor comprises indium gallium arsenide (InGaAs). 
     
     
         4 . The method of  claim 1 , wherein the sulfur passivation layer is formed by applying a thiourea containing solution. 
     
     
         5 . The method of  claim 4 , wherein the sulfur passivation layer is a monolayer in thickness. 
     
     
         6 . The method of  claim 1 , wherein the aluminum containing layer comprises aluminum oxide. 
     
     
         7 . The method of  claim 1 , wherein the aluminum containing layer is formed by atomic layer deposition (ALD). 
     
     
         8 . The method of  claim 5 , wherein the aluminum containing layer is a monolayer in thickness. 
     
     
         9 . The method of  claim 1 , wherein the metal oxide containing layer is formed by atomic layer deposition. 
     
     
         10 . The method of  claim 1 , wherein the metal oxide layer comprises zinc. 
     
     
         11 . The method of  claim 10 , wherein the metal oxide layer has an n-type conductivity. 
     
     
         12 . The method of  claim 1 , wherein the type III-V semiconductor material is doped to an n-type conductivity. 
     
     
         13 . The method of  claim 1 , wherein the metal contact is composed of a composition selected from aluminum, titanium, and combinations thereof. 
     
     
         14 . The method of  claim 1 , wherein a conduction band of the type III-V semiconductor material is substantially aligned with a conduction band of the metal oxide containing layer. 
     
     
         15 . A method of forming a device comprising:
 providing a region composed of indium gallium arsenide (InGaAs);   forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface the region of the type III-V semiconductor material to provide a passivated surface;   forming a metal oxide containing layer on the passivated surface, wherein a conduction band of the InGaAs is substantially aligned with a conduction band of the metal oxide containing layer; and   forming a metal contact is formed on the metal oxide containing layer.   
     
     
         16 . The method of  claim 15 , wherein a channel region of a field effect transistor for the device comprises indium gallium arsenide (InGaAs). 
     
     
         17 . A device comprising:
 an n-type conductivity region comprised of a type III-V semiconductor material; and   a contact to the n-type conductivity region, wherein the contact comprises a sulfur passivation layer atop the type III-V semiconductor material, and a metal oxide layer, wherein a conduction band of the type III-V semiconductor material is substantially aligned with a conduction band of the metal oxide containing layer.   
     
     
         18 . The device of  claim 17 , wherein the contact may further include a metal containing portion on the metal oxide containing layer. 
     
     
         19 . The device of  claim 17 , wherein the metal contact is composed of a composition selected from aluminum, titanium, and combinations thereof. 
     
     
         20 . The device of  claim 17 , wherein the type III-V semiconductor material is indium gallium arsenide (InGaAs).