Method of Manufacturing a Multi-Chip Semiconductor Power Device

Abstract

A method of manufacturing a semiconductor device includes mounting a first semiconductor power chip on a first carrier, mounting a second semiconductor power chip on a second carrier, bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip, and mounting a third semiconductor chip over the contact clip.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 mounting a first semiconductor power chip on a first carrier;   mounting a second semiconductor power chip on a second carrier;   bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip;   mounting a third semiconductor chip over the contact clip;   depositing a first bonding substance onto the first carrier;   placing the first semiconductor power chip on the first bonding substance;   depositing a second bonding substance onto the second carrier;   placing the second semiconductor power chip on second bonding substance;   depositing a third bonding substance onto the contact clip;   placing the third semiconductor chip on third bonding substance; and   wherein the mounting of the first, second and third chips comprises performing a single step of applying energy to the arrangement comprising the first, second and third semiconductor chip to reflow or cure each one of the first, second, and third bonding substances.   
     
     
         2 . The method of  claim 1 , wherein the first bonding substance, the second bonding substance and the third bonding substance each comprise a solder material. 
     
     
         3 . The method of  claim 1 , further comprising:
 applying a bond wire configured to electrically connect the third semiconductor chip to the first semiconductor power chip or to the second semiconductor power chip.   
     
     
         4 . The method of  claim 1 , further comprising:
 electrically connecting a chip load electrode of the first semiconductor power chip to a third carrier, wherein the third carrier is arranged next to the first carrier.   
     
     
         5 . The method of  claim 4 , wherein the third carrier is coplanar with the first carrier and the second carrier. 
     
     
         6 . The method of  claim 1 , wherein the third semiconductor chip is mounted over the contact clip in a face-up orientation in which electrodes of the third semiconductor chip are disposed on a surface of the third semiconductor chip opposite a surface of the third semiconductor chip which is mounted to the contact clip. 
     
     
         7 . The method of  claim 1 , wherein the contact clip has an extension in at least one lateral direction protruding beyond a laterally outer outline of the first semiconductor power chip, the method further comprising:
 electrically connecting the extension of the contact clip to a fourth carrier.   
     
     
         8 . The method of  claim 1 , further comprising:
 mounting a fourth semiconductor chip over the contact clip.   
     
     
         9 . The method of  claim 1 , further comprising:
 mounting a fourth semiconductor chip over the contact clip, wherein applying energy for mounting the first semiconductor power chip, the second semiconductor power chip and the third semiconductor chip also serves for mounting the fourth semiconductor chip.   
     
     
         10 . The method of  claim 1 , wherein the first carrier and the second carrier are electrically disconnected from each other. 
     
     
         11 . The method of  claim 1 , wherein the third semiconductor chip is a logic chip. 
     
     
         12 . The method of  claim 1 , further comprising:
 covering the first semiconductor power chip, the second semiconductor power chip, the contact clip and the third semiconductor chip at least partially with an encapsulation material.   
     
     
         13 . The method of  claim 12 , wherein a surface of the first carrier opposite the mounting surface of the first carrier or a surface of the second carrier opposite the mounting surface of the second carrier are exposed by the encapsulation material so as to form a leadless package external contact area.