Data storage device and parity code processing method thereof

Abstract

A data storage device and a parity code processing method thereof are provided. The data storage device includes a non-volatile memory and a controller. The controller includes a RAID ECC engine. The RAID ECC engine has a memory, wherein after completing an encoding operation on each N pages of user data to generate a corresponding parity code. The RAID ECC engine compresses the parity code and stores the compressed parity code in the memory, wherein after all K parity codes of the K×N pages of the user data are compressed and stored in the memory, the RAID ECC engine writes the compressed K parity codes to the non-volatile memory. As such, the frequency of switching the state of the RAID ECC engine is reduced, and the number and time of writing data to the non-volatile memory is reduced.

What is claimed is: 
     
         1 . A data storage device, comprising:
 a non-volatile memory; and   a controller, electrically coupled to the non-volatile memory and comprising:
 an access interface, coupled to a host and the non-volatile memory; 
 a central processing unit (CPU), used to interpret write/read commands issued by the host and control the access interface to access user data of the non-volatile memory; and 
 a redundant array of independent disks (RAID) error correcting code (ECC) engine, coupled to the non-volatile memory and used to perform an error correction procedure on the user data, wherein the error correction procedure is divided into an encoding operation or a decoding operation, the RAID ECC engine has a memory, wherein after completing the encoding operation on each N pages of the user data to generate a corresponding parity code, the RAID ECC engine compresses the parity code and stores the compressed parity code in the memory, wherein after all K parity codes of the K×N pages of the user data are compressed and stored in the memory, the RAID ECC engine writes the compressed K parity codes to the non-volatile memory, wherein K and N are both positive integers greater than one. 
   
     
     
         2 . The data storage device according to  claim 1 , wherein the controller further comprises:
 a data buffer, coupled to the access interface, the RAID ECC engine and the non-volatile memory, wherein the data buffer is used to temporarily store the user data from the host or the non-volatile memory.   
     
     
         3 . The data storage device according to  claim 2 , wherein the RAID ECC engine further comprises:
 a control register, coupled to the CPU and used to receive at least one control signal and temporary data from the CPU; and   a plurality of operational circuits, wherein each of the plurality of operational circuits comprises:
 an exclusive OR (XOR) logical operation unit; 
 a page buffer; and 
 a first selector, having two input ends and an output end, wherein the two input ends of the first selector are respectively coupled to an output end of the XOR logical operation unit and the control register, the output end of the first selector is coupled to the page buffer, wherein the CPU controls, by the control register, the first selector to determine an input source of the page buffer, so that the page buffer is used to store an operation result from the XOR logical operation unit or used to store the temporary data from the CPU. 
   
     
     
         4 . The data storage device according to  claim 3 , wherein the RAID ECC engine further comprises:
 a state machine, coupled to the control register and used to control the RAID ECC engine to perform the encoding operation or the decoding operation; and   a second selector, having a plurality of output ends and an input end, wherein the plurality of output ends of the second selector are respectively coupled to input ends of the plurality of operational circuits, the input end of the second selector is coupled to the data buffer or the non-volatile memory, wherein the CPU controls the second selector by the control register, so that the user data received by the input end of the second selector from the data buffer or the non-volatile memory is outputted to at least one of the specified plurality of operational circuits.   
     
     
         5 . A parity code processing method executed by a controller of a data storage device, wherein the data storage device further comprises a non-volatile memory electrically coupled to the controller, the controller comprises an access interface, a CPU and a RAID ECC engine, the access interface is coupled to a host and the non-volatile memory, the CPU is used to interpret write/read commands issued by the host and control the access interface to access user data of the non-volatile memory, and the parity code processing method comprises:
 configuring the CPU to issue at least one control signal to the RAID ECC engine and transmitting the user data of a plurality of pages to the RAID ECC engine;   configuring the RAID ECC engine to perform an encoding operation on the user data of N pages based on the control signal to generate a corresponding parity code, compress the parity code, and store the compressed parity code in a memory of the RAID ECC engine;   configuring the CPU to determine whether the user data of a super page group has been transmitted to the RAID ECC engine, wherein the user data of the super page group is referred to as the user data of K×N pages; and   when it is determined that the user data of the super page group has been transmitted to the RAID ECC engine, configuring the CPU to control the RAID ECC engine to write compressed K parity codes of the user data of the super page group to the non-volatile memory, wherein K and N are both positive integers greater than one.   
     
     
         6 . The parity code processing method according to  claim 5 , wherein the controller further comprises:
 a data buffer, coupled to the access interface, the RAID ECC engine and the non-volatile memory, wherein the data buffer is used to temporarily store the user data from the host or the non-volatile memory.   
     
     
         7 . The parity code processing method according to  claim 6 , wherein the RAID ECC engine comprises:
 a control register, coupled to the CPU and used to receive at least one control signal and temporary data from the CPU; and   a plurality of operational circuits, wherein each of the plurality of operational circuits comprises:
 an XOR logical operation unit; 
 a page buffer; and 
 a first selector, having two input ends and an output end, wherein the two input ends of the first selector are respectively coupled to an output end of the XOR logical operation unit and the control register, the output end of the first selector is coupled to the page buffer, wherein the CPU controls, by the control register, the first selector to determine an input source of the page buffer, so that the page buffer is used to store an operation result from the XOR logical operation unit, or used to store the temporary data from the CPU. 
   
     
     
         8 . The parity code processing method according to  claim 7 , wherein the RAID ECC engine further comprises:
 a state machine, coupled to the control register and used to control the RAID ECC engine to perform the encoding operation or a decoding operation; and   a second selector, having a plurality of output ends and an input end, wherein the plurality of output ends of the second selector are respectively coupled to input ends of the plurality of operational circuits, the input end of the second selector is coupled to the data buffer or the non-volatile memory, wherein the CPU controls the second selector by the control register, so that the user data received by the input end of the second selector from the data buffer or the non-volatile memory is outputted to at least one of the specified plurality of operational circuits.