US2020066352A1PendingUtilityA1
High voltage architecture for non-volatile memory
Assignee: Longitude Flash Memory Solutions LtdPriority: Jun 15, 2015Filed: Aug 5, 2019Published: Feb 27, 2020
Est. expiryJun 15, 2035(~8.9 yrs left)· nominal 20-yr term from priority
G11C 8/08G11C 16/16G11C 16/0433G11C 16/08G11C 16/30G11C 16/26G11C 7/18G11C 16/10G11C 16/14H01L 31/113H10F 30/2823
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Claims
Abstract
A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method comprising:
erasing, during an erase operation, a non-volatile memory cell of a memory device, wherein the erasing comprises:
applying a first high voltage signal to a common source line, wherein the common source line is shared among non-volatile memory cells of a sector of non-volatile memory cells, and the first high voltage signal is above a highest voltage of a power supply; and
applying the first high voltage signal to a local bit line.Join the waitlist — get patent alerts
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