Apparatus and method of clock shaping for memory

Abstract

A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

What is claimed is: 
     
         1 . A clock delay and gating circuit comprising:
 a first AND gate coupled to a clock enable signal and a write enable signal;   a first inverter coupled to the write enable signal;   a second AND gate coupled to the clock enable signal and to the first inverter;   a first clock gating cell coupled to a first clock signal and an output of the second AND gate;   a second clock gating cell coupled to the first clock signal and an output of the first AND gate;   a first inverter coupled to an output of the second clock gating cell;   a second inverter coupled to an output of the first inverter;   a third inverter coupled to an output of the second inverter; and   an OR gate coupled to an output of the first clock gating cell and an output of the third inverter.   
     
     
         2 . The clock delay and gating circuit of  claim 1 , wherein the first clock gating cell is configured to output a second clock signal to the OR gate when the output of the second AND gate is a logical high. 
     
     
         3 . The clock delay and gating circuit of  claim 2 , wherein the third inverter is configured to output a third clock signal to the OR gate when the output of the first AND gate is a logical high. 
     
     
         4 . The clock delay and gating circuit of  claim 3 , wherein the first clock signal has zero latency, the second clock signal has a first latency greater than zero, and the third clock signal has a second latency greater than the first latency. 
     
     
         5 . The clock delay and gating circuit of  claim 3 , wherein the OR gate is configured to output the third clock signal during a write operation and the second clock signal during a read operation. 
     
     
         6 . The clock delay and gating circuit of  claim 1 , wherein an output of the OR gate is coupled to a memory. 
     
     
         7 . The clock delay and gating circuit of  claim 6 , wherein the memory is a cache memory or a memory sub-system. 
     
     
         8 . The clock delay and gating circuit of  claim 6 , wherein the memory writes data to the memory using the third clock signal and reads data from the memory using the second clock signal. 
     
     
         9 . The clock delay and gating circuit of  claim 1 , wherein the clock delay and gating circuit is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and an automotive device in an automotive vehicle, and further includes the device. 
     
     
         10 . A clock delay and gating circuit comprising:
 first means for implementing a Boolean function coupled to a clock enable signal and a write enable signal;   a first inverter coupled to the write enable signal;   second means for implementing a Boolean function coupled to the clock enable signal and to the first inverter;   a first means for gating a clock coupled to a first clock signal and an output of the second means for implementing a Boolean function;   a second means for gating a clock coupled to the first clock signal and an output of the first means for implementing a Boolean function;   a first inverter coupled to an output of the second means for gating a clock;   a second inverter coupled to an output of the first inverter;   a third inverter coupled to an output of the second inverter; and   an OR gate coupled to an output of the first means for gating a clock and an output of the third inverter.   
     
     
         11 . The clock delay and gating circuit of  claim 10 , wherein the first means for gating a clock is configured to output a second clock signal to the OR gate when the output of the second means for implementing a Boolean function is a logical high. 
     
     
         12 . The clock delay and gating circuit of  claim 11 , wherein the third inverter is configured to output a third clock signal to the OR gate when the output of the first means for implementing a Boolean function is a logical high. 
     
     
         13 . The clock delay and gating circuit of  claim 12 , wherein the first clock signal has zero latency, the second clock signal has a first latency greater than zero, and the third clock signal has a second latency greater than the first latency. 
     
     
         14 . The clock delay and gating circuit of  claim 12 , wherein the OR gate is configured to output the third clock signal during a write operation and the second clock signal during a read operation. 
     
     
         15 . The clock delay and gating circuit of  claim 1 , wherein an output of the OR gate is coupled to a memory. 
     
     
         16 . The clock delay and gating circuit of  claim 15 , wherein the memory is a cache memory or a memory sub-system. 
     
     
         17 . The clock delay and gating circuit of  claim 15 , wherein the memory writes data to the memory using the third clock signal and reads data from the memory using the second clock signal. 
     
     
         18 . The clock delay and gating circuit of  claim 1 , wherein the clock delay and gating circuit is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and an automotive device in an automotive vehicle, and further includes the device. 
     
     
         19 . A memory circuit comprising:
 a first clock signal;   a write enable signal, the write enable signal has a polarity;   a clock delay circuit coupled to the first clock signal and the write enable signal, the clock delay circuit configured to output one of a second clock signal or a third clock signal based on the polarity of the write enable signal; and   a memory coupled to the clock delay circuit.   
     
     
         20 . The memory circuit of  claim 19 , wherein the clock delay circuit outputs the third clock signal during a write operation and the second clock signal during a read operation. 
     
     
         21 . The memory circuit of  claim 19 , wherein the clock delay circuit comprises:
 a latch circuit coupled to the first clock signal and the write enable signal, the latch circuit configured to output a latch output based on the polarity of the write enable signal;   a first AND gate coupled to the latch output and the first clock signal;   a second AND gate coupled to the first clock signal and to the latch output through a first inverter in series with a second inverter in series with a third inverter; and   an OR gate coupled to an output of the first AND gate and an output of the second AND gate, wherein the OR gate is coupled to the memory.   
     
     
         22 . The memory circuit of  claim 19 , wherein the clock delay circuit comprises:
 a first AND gate coupled to a clock enable signal and the write enable signal;   a first inverter coupled to the write enable signal;   a second AND gate coupled to the clock enable signal and to the first inverter;   a first clock gating cell coupled to the first clock signal and an output of the second AND gate;   a second clock gating cell coupled to the first clock signal and an output of the first AND gate;   a first inverter coupled to an output of the second clock gating cell;   a second inverter coupled to an output of the first inverter;   a third inverter coupled to an output of the second inverter; and   an OR gate coupled to an output of the first clock gating cell and an output of the third inverter, wherein the OR gate is coupled to the memory.   
     
     
         23 . A memory circuit comprising:
 a first clock signal;   a write enable signal, the write enable signal has a polarity;   means for delaying a clock coupled to the first clock signal and the write enable signal, the means for delaying a clock configured to output one of a second clock signal or a third clock signal based on the polarity of the write enable signal; and   a memory coupled to the means for delaying a clock.   
     
     
         24 . The memory circuit of  claim 23 , wherein the means for delaying a clock outputs the third clock signal during a write operation and the second clock signal during a read operation. 
     
     
         25 . The memory circuit of  claim 23 , wherein the means for delaying a clock comprises:
 a latch circuit coupled to the first clock signal and the write enable signal, the latch circuit configured to output a latch output based on the polarity of the write enable signal;   a first AND gate coupled to the latch output and the first clock signal;   a second AND gate coupled to the first clock signal and to the latch output through a first inverter in series with a second inverter in series with a third inverter; and   an OR gate coupled to an output of the first AND gate and an output of the second AND gate, wherein the OR gate is coupled to the memory.   
     
     
         26 . The memory circuit of  claim 23 , wherein the means for delaying a clock comprises:
 a first AND gate coupled to a clock enable signal and the write enable signal;   a first inverter coupled to the write enable signal;   a second AND gate coupled to the clock enable signal and to the first inverter;   a first clock gating cell coupled to the first clock signal and an output of the second AND gate;   a second clock gating cell coupled to the first clock signal and an output of the first AND gate;   a first inverter coupled to an output of the second clock gating cell;   a second inverter coupled to an output of the first inverter;   a third inverter coupled to an output of the second inverter; and   an OR gate coupled to an output of the first clock gating cell and an output of the third inverter, wherein the OR gate is coupled to the memory.